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ADC121S021 Arkusz danych(PDF) 3 Page - Texas Instruments |
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ADC121S021 Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 26 page PAD 1 V A CS 2 GND 5 SDATA 3 V IN 4 SCLK 6 1 V A CS 2 GND 5 SDATA 3 V IN 4 SCLK 6 3 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 Product Folder Links: ADC121S021 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated (1) All devices are fully pin and function compatible. 5 Device Comparison Table (1) RESOLUTION SPECIFIED FOR SAMPLE RATE RANGE OF: 50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps 12-bit ADC121S021 ADC121S051 ADC121S101 10-bit ADC101S021 ADC101S051 ADC101S101 8-bit ADC081S021 ADC081S051 ADC081S101 6 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View See package number DBV0006A. NGF Package 6-Pin WSON Top View See package number NGF0006A. Pin Functions PIN TYPE DESCRIPTION NAME NO. CS 6 Digital I/O Chip select. On the falling edge of CS, a conversion process begins. GND 2 PWR The ground return for the supply and signals. SCLK 4 Digital I/O Digital clock input. This clock directly controls the conversion and readout processes. SDATA 5 Digital I/O Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. VA 1 PWR Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin. VIN 3 Analog I/O Analog input. This signal can range from 0 V to VA. PAD — PWR For package suffix CISD(X) only, TI recommends connecting the center pad to ground. |
Podobny numer części - ADC121S021 |
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Podobny opis - ADC121S021 |
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