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ADC104S021Q-Q1 Arkusz danych(PDF) 5 Page - Texas Instruments

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Numer części ADC104S021Q-Q1
Szczegółowy opis  4-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

ADC104S021Q-Q1 Arkusz danych(HTML) 5 Page - Texas Instruments

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ADC104S021
www.ti.com
SNAS278H – FEBRUARY 2005 – REVISED MARCH 2013
ADC104S021/ADC104S021Q Converter Electrical Characteristics
(1)(2) (continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits (3)
Units
IOZH, IOZL TRI-STATE® Leakage Current
±0.01
±1
µA (max)
COUT
TRI-STATE® Output Capacitance
2
4
pF (max)
Output Coding
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
2.7
V (min)
VA
Supply Voltage
5.25
V (max)
VA = +5.25V,
1.3
1.8
mA (max)
fSAMPLE = 200 ksps, fIN = 40 kHz
Supply Current, Normal Mode
(Operational, CS low)
VA = +3.6V,
0.55
0.7
mA (max)
fSAMPLE = 200 ksps, fIN = 40 kHz
IA
VA = +5.25V,
90
nA
fSAMPLE = 0 ksps
Supply Current, Shutdown (CS high)
VA = +3.6V,
32
nA
fSAMPLE = 0 ksps
VA = +5.25V
6.9
9.5
mW (max)
Power Consumption, Normal Mode
(Operational, CS low)
VA = +3.6V
1.94
2.5
mW (max)
PD
VA = +5.25V
0.47
µW
Power Consumption, Shutdown (CS
high)
VA = +3.6V
0.12
µW
AC ELECTRICAL CHARACTERISTICS
0.8
MHz (min)
fSCLK
Clock Frequency
(4)
3.2
MHz (max)
50
ksps (min)
fS
Sample Rate
(4)
200
ksps (max)
tCONV
Conversion Time
13
SCLK cycles
30
% (min)
DC
SCLK Duty Cycle
fSCLK = 3.2 MHz
50
70
% (max)
tACQ
Track/Hold Acquisition Time
Full-Scale Step Input
3
SCLK cycles
Throughput Time
Acquisition Time + Conversion Time
16
SCLK cycles
(4)
This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is
specified under Operating Ratings.
ADC104S021/ADC104S021Q Timing Specifications
(1)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits (2)
Units
VA = +3.0V
−3.5
tCSU
Setup Time SCLK High to CS Falling Edge
(3)
10
ns (min)
VA = +5.0V
−0.5
VA = +3.0V
+4.5
tCLH
Hold time SCLK Low to CS Falling Edge
(3)
10
ns (min)
VA = +5.0V
+1.5
VA = +3.0V
+4
tEN
Delay from CS Until DOUT active
30
ns (max)
VA = +5.0V
+2
VA = +3.0V
+16.5
tACC
Data Access Time after SCLK Falling Edge
30
ns (max)
VA = +5.0V
+15
tSU
Data Setup Time Prior to SCLK Rising Edge
+3
10
ns (min)
(1)
PPAP (Production part Approval Process) documentation of the device technology, process and qualification is available from Texas
Instruments upon request.
(2)
Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3)
Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.
Copyright © 2005–2013, Texas Instruments Incorporated
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