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ADS5463-EP Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS5463-EP Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 32 page ADS5463-EP www.ti.com ......................................................................................................................................... SGLS382C – NOVEMBER 2006 – REVISED OCTOBER 2009 TIMING CHARACTERISTICS (1) Typical values at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tA Aperture delay 200 ps Aperture jitter, rms 160 fs Latency 3.5 cycles tCLK Clock period 2 ns tCLKH Clock pulse duration, high 1 ns tCLKL Clock pulse duration, low 1 ns tDRY CLK to DRY delay(1) Zero crossing, 7 pF diff loading 1100 ps tDATA CLK to DATA/OVR delay (1) Zero crossing, 7 pF diff loading 1100 ps tSKEW DRY to DATA skew tDATA – tDRY, 7 pF diff loading 0 ps tRISE DRY/DATA/OVR rise time 7 pF differential loading 500 ps tFALL DRY/DATA/OVR fall time 7 pF differential loading 500 ps (1) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the data propagation delay. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :ADS5463-EP |
Podobny numer części - ADS5463-EP_14 |
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Podobny opis - ADS5463-EP_14 |
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