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ADS5521IPAPR Arkusz danych(PDF) 11 Page - Texas Instruments

Numer części ADS5521IPAPR
Szczegółowy opis  12-Bit, 105MSPS Analog-To-Digital Converter
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

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ADS5521
www.ti.com ...................................................................................................................................................... SBAS309D – MAY 2004 – REVISED OCTOBER 2008
PIN ASSIGNMENTS(1)
TERMINAL
NO. OF
NAME
NO.
PINS
I/O
DESCRIPTION
5, 7, 9, 15, 22,
AVDD
24, 26, 28, 33,
12
I
Analog power supply
34, 37, 39
6, 8, 12, 13,
14, 16, 18, 21,
AGND
14
I
Analog ground
23, 25, 27, 32,
36, 38
DRVDD
49, 58
2
I
Output driver power supply
1, 42, 48, 50,
DRGND
6
I
Output driver ground
57, 59
NC
44, 45
2
Not connected
INP
19
1
I
Differential analog input (positive)
INM
20
1
I
Differential analog input (negative)
REFP
29
1
O
Reference voltage (positive); 1-
µF capacitor in series with a 1-Ω resistor to GND
REFM
30
1
O
Reference voltage (negative); 1-
µF capacitor in series with a 1-Ω resistor to GND
IREF
31
1
I
Current set; 56-k
Ω resistor to GND; do not connect capacitors
CM
17
1
O
Common-mode output voltage
RESET
35
1
I
Reset (active high), 200-k
Ω resistor to AVDD
(2)
OE
41
1
I
Output enable (active high)(3)
DFS
40
1
I
Data format and clock out polarity select(4)(3)
CLKP
10
1
I
Data converter differential input clock (positive)
CLKM
11
1
I
Data converter differential input clock (negative)
SEN
4
1
I
Serial interface chip select(3)
SDATA
3
1
I
Serial interface data(3)
SCLK
2
1
I
Serial interface clock(3)
D0 (LSB) to
46, 47, 51-56,
14
O
Parallel data output
D11 (MSB)
60-63
OVR
64
1
O
Over-range indicator bit
CLKOUT
43
1
O
CMOS clock out in sync with data
(1)
PowerPAD is connected to analog ground.
(2)
If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details.
(3)
Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
(4)
Table 4 defines the voltage levels for each mode selectable via the DFS pin.
Copyright © 2004–2008, Texas Instruments Incorporated
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