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ADS5525IRGZTG4 Arkusz danych(PDF) 8 Page - Texas Instruments

Numer części ADS5525IRGZTG4
Szczegółowy opis  12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
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Strona internetowa  http://www.ti.com
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ADS5525
SLWS191B – JULY 2006 – REVISED MAY 2007
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DDR LVDS MODE(4)
tsu
Data setup time(5)
Data valid (6) to zero-cross of CLKOUTP
1.3
1.8
ns
Zero-cross of CLKOUTP to data becoming
th
Data hold time(5)
0.5
1.0
ns
invalid(6)
Input clock rising edge zero-cross to output
tPDI
Clock propagation delay
3.9
4.6
5.3
ns
clock rising edge zero-cross
Duty cycle of differential clock,
LVDS bit clock duty cycle
(CLKOUTP-CLKOUTM)
50%
80
≤ Fs ≤ 170 MSPS
Rise time measured from –50 mV to 50 mV
tr,
Data rise time,
Fall time measured from 50 mV to –50 mV
50
100
200
ps
tf
Data fall time
1
≤ Fs ≤ 170 MSPS
Rise time measured from –50 mV to 50 mV
tCLKRISE,
Output clock rise time,
Fall time measured from 50 mV to –50 mV
50
100
200
ps
tCLKFALL
Output clock fall time
1
≤ Fs ≤ 170 MSPS
Output enable (OE) to valid
tOE
Time to valid data after OE becomes active
1
µs
data delay
PARALLEL CMOS MODE
tsu
Data setup time (5)
Data valid(7) to 50% of CLKOUT rising edge
2.5
3.3
ns
50% of CLKOUT rising edge to data
th
Data hold time (5)
0.8
1.2
ns
becoming invalid(7)
Input clock rising edge zero-cross to 50% of
tPDI
Clock propagation delay
1.9
2.7
3.5
ns
CLKOUT rising edge
Duty cycle of output clock (CLKOUT)
Output clock duty cycle
45%
80
≤ Fs ≤ 170 MSPS
Rise time measured from 20% to 80% of
DRVDD
tr,
Data rise time,
Fall time measured from 80% to 20% of
0.8
1.5
2
ns
tf
Data fall time
DRVDD
1
≤ Fs ≤ 170 MSPS
Rise time measured from 20% to 80% of
DRVDD
tCLKRISE,
Output clock rise time,
Fall time measured from 80% to 20% of
0.4
0.8
1.2
ns
tCLKFALL
Output clock fall time
DRVDD
1
≤ Fs ≤ 170 MSPS
Output enable (OE) to valid
tOE
Time to valid data after OE becomes active
50
ns
data delay
(4)
Measurements are done with a transmission line of 100
Ω characteristic impedance between the device and the load.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margin.
(6)
Data valid refers to logic high of +50 mV and logic low of –50 mV.
(7)
Data valid refers to logic high of 2 V and logic low of 0.8 V
8
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