 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
ADS127L01 Arkusz danych(PDF) 10 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
ADS127L01 Arkusz danych(HTML) 10 Page - Texas Instruments |
|
|
10 / 86 page  10 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Product Folder Links: ADS127L01 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) CS can be tied low permanently in case the serial bus is not shared with any other device. (2) See the SPI Timeout section for more information. 6.6 Timing Requirements: Serial Interface over operating ambient temperature range (unless otherwise noted) 2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V UNIT MIN TYP MAX MIN TYP MAX tc(CLK) Master clock period HR mode 57 10,000 57 10,000 ns LP mode 114 10,000 114 10,000 VLP mode 227 10,000 227 10,000 tw(CP) Master clock high and low pulse duration HR mode 28 5,000 28 5,000 ns LP mode 56 5,000 56 5,000 VLP mode 112 5,000 112 5,000 td(CSSC) Delay time, CS falling edge to first SCLK rising edge(1) 8 12 ns tc(SC) SCLK period 40 6250 50 6250 ns tw(SCHL) Pulse duration, SCLK high or low 20 25 ns tsu(DI) Setup time, DIN valid before SCLK falling edge 6 9 ns th(DI) Hold time, DIN valid after SCLK falling edge 8 9 ns tw(CSH) Pulse duration, CS high 6 6 tCLK td(SCCS) Delay time, final SCLK falling edge to CS rising edge 2 2 tCLK td(DECODE) Delay time, command decode time 4 4 tCLK SPI timeout(2) TOUT_DEL = 0 216 216 tCLK TOUT_DEL = 1 214 214 tCLK tsu(DCI) Setup time, DAISYIN valid before SCLK falling edge 5 8 ns th(DCI) Hold time, DAISYIN valid after SCLK falling edge 20 25 ns 6.7 Switching Characteristics: Serial Interface over operating free-air temperature range (unless otherwise noted) 2.8 V < DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.8 V UNIT MIN TYP MAX MIN TYP MAX tp(CSDO) Propagation delay time CS falling edge to DOUT driven 12 18 ns tp(SCDO) Propagation delay time SCLK rising edge to valid new DOUT 15 21 ns tv(DO) Valid time, SCLK falling edge to DOUT invalid 18 tSCLK / 2 20 tSCLK / 2 ns tp(CSDOZ) Propagation delay time CS rising edge to DOUT high impedance 20 20 ns |
Podobny numer części - ADS127L01 |
|
Podobny opis - ADS127L01 |
|
|
Link URL |
| Polityka prywatności |
| ALLDATASHEET.PL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
