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ADS774H Arkusz danych(PDF) 11 Page - Texas Instruments |
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ADS774H Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 27 page THEORY OF OPERATION OVERVIEW CONVERSION SAMPLING C R G 2C R G 4C R G + - Comparator Reference Input S Signal Analog Input Out S 1 S 2 S 3 S C ADS774H www.ti.com ................................................................................................................................................................................................ SBAS443 – AUGUST 2009 In the ADS774H, the advantages of advanced CMOS When a conversion command is received, switch S1 technology (such as high logic density, stable opens to capture a charge on the MSB capacitor capacitors, and precision analog switches) produce a proportional to the analog input level at the time of fast, low-power ADC with internal sample/hold. the sampling command, and switch SC opens to float the comparator input. The charge held in the The charge-redistribution successive-approximation capacitor array can now be moved between the three circuitry converts analog input voltages into digital capacitors in the array by connecting switches S1, S2, words. and S3 to either the R position (to connect to the reference) or the G position (to connect to GND), thus A simple example of a charge-redistribution ADC with changing the voltage generated at the comparator only three bits is shown in Figure 11. input. During the first approximation, the MSB capacitor is connected through switch S1 to the reference, while While sampling, the capacitor array switch for the switches S2 and S3 are connected to GND. MSB capacitor (S1) is in position S, so that the Depending on whether the comparator output is high charge on the MSB capacitor is proportional to the or low, the logic then latches S1 in position R or G. voltage level of the analog input signal. The Similarly, the second approximation is made by remaining array switches (S2 and S3) are set to connecting S2 to the reference and S3 to GND, and position G. Switch SC is closed, setting the latching S2 according to the output of the comparator. comparator input offset to zero. After three successive approximation steps have been made, the voltage level at the comparator is within 1/2LSB of GND, and a digital word that represents the analog input can be determined from the positions of S1, S2 and S3. Figure 11. 3-Bit Charge Redistribution ADC Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 |
Podobny numer części - ADS774H_13 |
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Podobny opis - ADS774H_13 |
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