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ADS1218 Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS1218 Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 45 page www.ti.com TIMING SPECIFICATIONS t 4 MSB (Command or Command and Data) LSB t 5 t 1 t 3 CS SCLK (POL = 0) D IN D OUT NOTE: (1) Bit Order = 0. t 7 MSB(1) LSB(1) t 8 t 10 t 2 t 2 t 11 t 6 t 9 SCLK (POL = 1) TIMING SPECIFICATION TABLE ADS1218 SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 SPEC DESCRIPTION MIN MAX UNIT t1 SCLK Period 4 tOSC Periods 3 DRDY Periods t2 SCLK Pulse Width, High and Low 200 ns t3 CS Low to first SCLK Edge; Setup Time 0 ns t4 DIN Valid to SCLK Edge; Setup Time 50 ns t5 Valid DIN to SCLK Edge; Hold Time 50 ns t6 Delay between last SCLK edge for DIN and first SCLK edge for DOUT: RDATA, RDATAC, RREG, WREG, RRAM 50 tOSC Periods CSREG, CSRAMX, CSRAM 200 tOSC Periods CSARAM, CSARAMX 1100 tOSC Periods t7(1) SCLK Edge to Valid New DOUT 50 ns t8(1) SCLK Edge to DOUT, Hold Time 0 ns t9 Last SCLK Edge to DOUT Tri-State 6 10 tOSC Periods NOTE: DOUT goes tri-state immediately when CS goes High. t10 CS Low time after final SCLK edge 0 ns t11 Final SCLK edge of one op code until first edge SCLK of next command: RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, CSARAM, 4 tOSC Periods CSREG, SLEEP, RDATA, RDATAC, STOPC DSYNC 16 tOSC Periods CSFL 33,000 tOSC Periods CREG, CRAM 220 tOSC Periods RF2R 1090 tOSC Periods CREGA 1600 tOSC Periods WR2F 76,850 (SPEED = 0) tOSC Periods 101,050 (SPEED = 1) 4 tOSC Periods SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods SELFCAL 14 DRDY Periods RESET (Command, SCLK, or Pin) 2640 tOSC Periods (1) Load = 20pF | | 10k Ω to DGND. 9 |
Podobny numer części - ADS1218 |
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Podobny opis - ADS1218 |
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