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ADS1282HIPW Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS1282HIPW Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 61 page 9 ADS1282-SP www.ti.com SBAS691 – MARCH 2016 Product Folder Links: ADS1282-SP Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Timing Requirements (continued) At TA = –55°C to 125°C and DVDD = 1.65 to 3.6 V, unless otherwise noted. MIN MAX UNIT tSCDL Final SCLK rising edge of command to first SCLK rising edge for register read/write data 24 1 / ƒCLK (1) Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization. 7.6 Pulse-Sync Timing Requirements See Figure 46 and Figure 47 for timing diagrams. MIN MAX UNIT tSYNC SYNC period(1) 1 Infinite n / ƒDATA tCSHD CLK to SYNC hold time to not latch on CLK edge 10 ns tSCSU SYNC to CLK setup time to latch on CLK edge 10 ns tSPWH, L SYNC pulse width, high or low 2 1 / ƒCLK tDR Time for data ready (SINC filter) See Device Support, Table 21 Time for data ready (FIR filter) 62.98046875 / ƒDATA + 466 / ƒCLK 7.7 Reset Timing Requirements See Figure 48 for timing diagram. MIN MAX UNIT tCRHD CLK to RESET hold time 10 ns tRCSU RESET to CLK setup time 10 ns tRST RESET low 2 1 / ƒCLK tDR Time for data ready 62.98046875 / ƒDATA + 468 / ƒCLK s (1) Load on DOUT = 20 pF || 100 k Ω. 7.8 Read Data Timing Requirements MIN MAX UNIT tDDPD DRDY to valid MSB on DOUT propagation delay (see Figure 54)(1) 100 ns tDR Time for new data after data read command (see Figure 55) 0 1 ƒDATA (1) At DC. See Figure 42. 7.9 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Group delay(1) Minimum phase filter 5 / ƒDATA s Linear phase filter 31 / ƒDATA s Settling time (latency) Minimum phase filter 62 / ƒDATA s Linear phase filter 62 / ƒDATA s |
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