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ADS900 Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS900 Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 16 page ADS900 9 SBAS058A The pipelined quantizer architecture has 9 stages with each stage containing a two-bit quantizer and a two bit Digital- to-Analog Converter (DAC), as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the sub- clock, which is the same frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique provides the ADS900 with excellent differential linearity and guarantees no missing codes at the 10-bit level. The ADS900 includes an internal reference circuit that provides the bias voltages for the internal stages (for details see “Internal Reference”). A midpoint voltage is established by the built-in resistor ladder that is made available at pin 26 “CM”. This voltage can be used to bias the inputs up to the recommended common-mode voltage or used to level shift the input driving circuitry. The ADS900 can be used in both a single-ended or differential input configuration. When operated in single-ended mode, the reference midpoint (pin 26) should be tied to the inverting input, pin 24. To accommodate a bipolar signal swing, the ADS900 oper- ates with a common-mode voltage (VCM) which is derived from the internal references. Due to the symmetric resistor ladder inside the ADS900, the VCM is situated between the top and bottom reference voltage. The following equation can be used for calculating the common-mode voltage level. VCM = (REFT +REFB)/2 (1) DIGITAL OUTPUT DATA The 10-bit output data is provided at CMOS logic levels. There is a 5.0 clock cycle data latency from the start convert signal to the valid output data. The standard output coding is Straight Offset Binary where a full scale input signal corresponds to all “1’s” at the output. The digital outputs of the ADS900 can be set to a high impedance state by driving the OE (pin 16) with a logic “HI”. Normal operation is achieved with pin 16 “LO” or Floating due to internal pull- down resistor. This function is provided for testability purposes but is not recommended to be used dynamically. The capacitive loading on the digital outputs should be kept below 15pF. APPLICATIONS DRIVING THE ANALOG INPUTS Figure 3 shows an example of an ac-coupled, single-ended interface circuit using high-speed op amps that operate on dual supplies (OPA650, OPA658, OPA680 and OPA681). The common-mode reference voltage (VCM), here +1.5V, biases the bipolar, ground-referenced input signal. The ca- pacitor C1 and resistor R1 form a high-pass filter with the –3dB frequency set at f–3dB = 1/(2 π R1 C1)(2) TABLE I. Coding Table for the ADS900. +FS (IN = +2V) 1111111111 +FS –1LSB 1111111111 +FS –2LSB 1111111110 +3/4 Full Scale 1110000000 +1/2 Full Scale 1100000000 +1/4 Full Scale 1010000000 +1LSB 1000000001 Bipolar Zero (IN +1.5V) 1000000000 –1LSB 0111111111 –1/4 Full Scale 0110000000 –1/2 Full Scale 0100000000 –3/4 Full Scale 0010000000 –FS +1LSB 0000000001 –FS (IN = +1V) 0000000000 STRAIGHT OFFSET BINARY (SOB) SINGLE-ENDED INPUT PIN 12 (IN = 1.5V DC) FLOATING or LO FIGURE 3. AC-Coupled Driver. The values for C1 and R1 are not critical in most applications and can be set freely. The values shown correspond to a –3dB corner frequency of 1.6kHz. Figure 4 depicts a circuit that can be used in single-supply applications. The common-mode voltage biases the op amp up to the appropriate common-mode voltage, for example VCM = +1.5V. With the use of capacitor CG the DC gain for the non-inverting op amp input is set to +1V/V. As a result the transfer function is modified to VOUT = VIN {(1 + RF/RG) + VCM}(3) Again, the input coupling capacitor C1 and resistor R1 form a high-pass filter. At the same time the input impedance is defined by R1. Resistor RS isolates the op amp’s output from the capacitive load to avoid gain peaking or even oscillation. It can also be used to establish a defined roll-off for the wideband noise. Its value is usually between 10 Ω and 100Ω. DIFFERENTIAL MODE OF OPERATION Some minor performance improvements in SFDR and THD can be realized by operating the ADS900 in its optional differential configuration. A RF-transformer with a center tap provides the best method of performing a single-ended to differential conversion and interface directly to the ADS900. 402 Ω OPA65x OPA68x V IN 402 Ω R 1 1k Ω V CM C 1 0.1µF 0.1µF IN IN 1.5V CM +5V R S –5V +3V ADS900 |
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