ADS902

11

SBAS063A

POWER-DOWN MODE

The ADS902’s low power consumption can be reduced even

further by initiating a power-down mode. To do so, the

Pwrdn-Pin (Pin 17) must be tied to a logic “High” reducing

the current drawn from the supply by about 88%. In normal

operation the power-down mode is disabled by an internal

pull-down resistor (50k

Ω).

During power-down, the digital outputs are set into the high-

impedance condition (3-state). With the clock applied, the

converter does not accurately process the sampled signal.

After removing the power-down condition the output data

from the following 5 clock cycles is invalid (data latency).

DECOUPLING AND GROUNDING

CONSIDERATIONS

The ADS902 converter has several supply pins, one of

which is dedicated to supply only the output driver. The

remaining supply pins are not, as is often the case, divided

into analog and digital supply pins since they are internally

connected on the chip. For this reason it is recommended to

treat the converter as an analog component and to power it

from the analog supply only. Digital supply lines often carry

high levels of noise which can couple back into the converter

and limit the achievable performance.

Because of the pipeline architecture, the converter also

generates high frequency transients and noise that are fed

back into the supply and reference lines. This requires that

the supply and reference pins be sufficiently bypassed.

Figure 9 shows the recommended decoupling scheme for the

analog supplies. In most cases 0.1

µF ceramic chip capacitors

are adequate to keep the impedance low over a wide fre-

quency range. Their effectiveness largely depends on the

proximity to the individual supply pin. Therefore, they

should be located as close to the supply pins as possible.

FIGURE 9. Recommended Bypassing for Analog Supply

Pins.

+V

S

1

13

14

GND

ADS902

0.1µF

+V

S

18

19

20

GND

0.1µF

+V

S

28

0.1µF