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ADS7844EB Arkusz danych(PDF) 11 Page - Texas Instruments |
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ADS7844EB Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 22 page ADS7844 11 SBAS100A www.ti.com FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. 1 DCLK CS 81 11 DOUT BUSY S DIN CONTROL BITS S CONTROL BITS 10 98765 4 3210 11 10 9 81 1 8 FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated serial port. Bit 7 Bit 0 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) SA2 A1 A0 — SGL/DIF PD1 PD0 TABLE III. Order of the Control Bits in the Control Byte. TABLE IV. Descriptions of the Control Bits within the Control Byte. BIT NAME DESCRIPTION 7 S Start Bit. Control byte starts with first HIGH bit on DIN. A new control byte starts with every 15th clock cycle. 6 - 4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit, these bits control the setting of the multiplexer input as detailed in Tables I and II. 3 — Not Used. 2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits A2 - A0, this bit controls the setting of the multiplexer input as detailed in Tables I and II. 1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for details. The SGL/DIF bit controls the multiplexer input mode: either single-ended (HIGH) or differential (LOW). In single-ended mode, the selected input channel is referenced to the COM pin. In differential mode, the two selected inputs provide a differential input. See Tables I and II and Figure 2 for more information. The last two bits (PD1 - PD0) select the power- down mode as shown in Table V. If both inputs are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid. 16-Clocks per Conversion The control bits for conversion n+1 can be overlapped with conversion ‘n’ to allow for a conversion every 16 clock cycles, as shown in Figure 4. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter. This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the input sample/hold may droop enough to affect the conversion result. In addition, the ADS7844 is fully powered while other serial communica- tions are taking place. t ACQ Acquire Idle Conversion Idle 1 DCLK CS 81 11 DOUT BUSY (MSB) (START) (LSB) A2 S DIN A1 A0 SGL/ DIF PD1 PD0 10 98765 4 3210 Zero Filled... 81 8 |
Podobny numer części - ADS7844EB |
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Podobny opis - ADS7844EB |
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