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74AHCT16373DGGRG4 Arkusz danych(PDF) 10 Page - Texas Instruments |
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74AHCT16373DGGRG4 Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 22 page 1OE 1LE 1D1 To Seven Other Channels 1Q1 2OE 2LE 2D1 2Q1 To Seven Other Channels C1 1D C1 1D SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com 9 Detailed Description 9.1 Overview The SNxAHCT16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, IO ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagrams Figure 3. Logic Diagram (Positive Logic) 10 Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 |
Podobny numer części - 74AHCT16373DGGRG4 |
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Podobny opis - 74AHCT16373DGGRG4 |
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