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AM5K2E04XABDA4 Arkusz danych(PDF) 6 Page - Texas Instruments

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Numer części AM5K2E04XABDA4
Szczegółowy opis  AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

AM5K2E04XABDA4 Arkusz danych(HTML) 6 Page - Texas Instruments

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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
AM5K2E0x Features and Description
............... 1
8.1
Device Boot
........................................ 129
1.1
Features
.............................................. 1
8.2
Device Configuration
............................... 148
1.2
Applications
........................................... 2
9
Device Operating Conditions
....................... 175
1.3
KeyStone II Architecture
.............................. 2
9.1
Absolute Maximum Ratings
........................ 175
1.4
Device Description
................................... 2
9.2
Recommended Operating Conditions
............. 176
1.5
Enhancements in KeyStone II
........................ 3
9.3
Electrical Characteristics
........................... 177
1.6
Functional Block Diagram
............................ 4
9.4
Power Supply to Peripheral I/O Mapping
.......... 178
2
Revision History
......................................... 7
10
AM5K2E0x Peripheral Information and Electrical
Specifications
......................................... 179
3
Device Characteristics
.................................. 8
10.1
Recommended Clock and Control Signal Transition
3.1
ARM CorePac
........................................ 9
Behavior
............................................ 179
3.2
Development Tools
.................................. 10
10.2
Power Supplies
.................................... 179
3.3
Device Nomenclature
............................... 10
10.3
Power Sleep Controller (PSC)
..................... 187
3.4
Related Documentation from Texas Instruments
... 12
10.4
Reset Controller
.................................... 193
3.5
Related Links
........................................ 13
10.5
Core PLL (Main PLL), DDR3 PLL, NETCP PLL and
3.6
Community Resources
.............................. 13
the PLL Controllers
................................ 198
3.7
Trademarks
.......................................... 13
10.6
DDR3 PLL
.......................................... 212
3.8
Electrostatic Discharge Caution
..................... 13
10.7
NETCP PLL
........................................ 214
3.9
Glossary
............................................. 13
10.8
DDR3 Memory Controller
.......................... 216
4
ARM CorePac
........................................... 14
10.9
I2C Peripheral
...................................... 217
4.1
Features
............................................. 16
10.10
SPI Peripheral
.................................... 221
4.2
System Integration
.................................. 16
10.11
HyperLink Peripheral
............................. 224
4.3
ARM Cortex-A15 Processor
......................... 16
10.12
UART Peripheral
................................. 226
4.4
CFG Connection
.................................... 18
10.13
PCIe Peripheral
................................... 227
4.5
Main TeraNet Connection
........................... 18
10.14
Packet Accelerator
............................... 227
4.6
Clocking and Reset
................................. 19
10.15
Security Accelerator
.............................. 228
5
Terminals
................................................ 20
10.16
Network Coprocessor Gigabit Ethernet (GbE)
Switch Subsystem
................................. 228
5.1
Package Terminals
.................................. 20
10.17
SGMII/XFI Management Data Input/Output
5.2
Pin Map
............................................. 20
(MDIO)
............................................. 230
5.3
Terminal Functions
.................................. 25
10.18
Ten-Gigabit Ethernet (10GbE) Switch
5.4
Pullup/Pulldown Resistors
.......................... 53
Subsystem
......................................... 231
6
Memory, Interrupts, and EDMA for AM5K2E0x
.. 55
10.19
Timers
............................................. 231
6.1
Memory Map SummaryAM5K2E0x
................. 55
10.20
General-Purpose Input/Output (GPIO)
........... 232
6.2
Memory Protection Unit (MPU) for AM5K2E0x
..... 64
10.21
Semaphore2
...................................... 233
6.3
Interrupts for AM5K2E0x
............................ 77
10.22
Universal Serial Bus 3.0 (USB 3.0)
............... 233
6.4
Enhanced Direct Memory Access (EDMA3)
10.23
TSIP Peripheral
................................... 234
Controller
........................................... 103
10.24
Universal Subscriber Identity Module (USIM)
.... 236
7
System Interconnect
................................. 114
10.25
EMIF16 Peripheral
................................ 236
7.1
Internal Buses and Switch Fabrics
................ 114
10.26
Emulation Features and Capability
............... 239
7.2
Switch Fabric Connections Matrix - Data Space
.. 114
10.27
Debug Port (EMUx)
............................... 241
7.3
Switch Fabric Connections Matrix - Configuration
11
Mechanical Data
...................................... 248
Space
.............................................. 120
11.1
Thermal Data
...................................... 248
7.4
Bus Priorities
....................................... 128
11.2
Packaging Information
............................. 248
8
Device Boot and Configuration
.................... 129
6
Table of Contents
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