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DAC37J84IAAVR Arkusz danych(PDF) 1 Page - Texas Instruments |
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DAC37J84IAAVR Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 122 page DAC37J84/DAC38J84 16-bit DAC 16-bit DAC 16-bit DAC 16-bit DAC xN xN xN xN RF RF Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DAC37J84, DAC38J84 SLASE17B – JANUARY 2014 – REVISED MARCH 2014 DAC3xJ84 Quad-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface 1 Features 3 Description The terminal-compatible DAC37J84/DAC38J84 family 1 • Resolution: 16-Bit is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS • Maximum Sample Rate: digital to analog converter (DAC) with JESD204B – DAC37J84: 1.6 GSPS interface. – DAC38J84: 2.5 GSPS Digital data is input to the device through 1, 2, 4 or 8 • Maximum Input Data Rate: 1.23GSPS configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and • JESD204B Interface programmable equalization. The interface allows – 8 JESD204B Serial Input Lanes JESD204B Subclass 1 SYSREF based deterministic – 12.5 Gbps Maximum Bit Rate per Lane latency and full synchronization of multiple devices. – Subclass 1 Multi-DAC Synchronization The device includes features that simplify the design • On-Chip Very Low Jitter PLL of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of • Selectable 1x -16x Interpolation stop-band attenuation simplify the data interface and • Independent Complex Mixers with 48-bit NCO/ or reconstruction filters. An on-chip 48-bit Numerically ±n×Fs/8 Controlled Oscillator (NCO) and independent • Wideband Digital Quadrature Modulator complex mixers allow flexible and accurate carrier Correction placement. • Sinx/x Correction Filters A high-performance low jitter PLL simplifies clocking of the device without significant impact on the • Fractional Sample Group Delay Correction dynamic range. The digital Quadrature Modulator • Multi-Band Mode: Digital Summation of Correction (QMC) and Group Delay Correction (QDC) Independent Complex Signals enable complete IQ compensation for gain, offset, • 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V phase, and group delay between channels in direct • Integrated Temperature Sensor up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to • JTAG Boundary Scan provide PA protection in cases when the abnormal • Terminal-Compatible with Dual-Channel power behavior of the input data is detected. DAC37J82/DAC38J82 Family • Power Dissipation: 1.8W at 2.5GSPS Device Information ORDER NUMBER PACKAGE BODY SIZE • Package: 10x10mm, 144-Ball Flip-Chip BGA DAC37J84IAAV FCBGA (144) 10 mm x 10 mm 2 Applications DAC38J84IAAV FCBGA (144) 10 mm x 10 mm • Cellular Base Stations • Diversity Transmit • Wideband Communications • Direct Digital Synthesis (DDS) instruments • Millimeter/Microwave Backhaul • Automated Test Equipment • Cable Infrastructure 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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