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CD54AC138F3A Arkusz danych(PDF) 1 Page - Texas Instruments

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Numer części CD54AC138F3A
Szczegółowy opis  3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
Download  17 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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CD54AC138F3A Arkusz danych(HTML) 1 Page - Texas Instruments

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CD54AC138, CD74AC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCHS328A – JANUARY 2003 – REVISED FEBRUARY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
D Balanced Propagation Delays
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The ’AC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing
applications that require very short propagation-delay times. In high-performance memory systems, these
decoders can be used to minimize the effects of system decoding. When employed with high-speed memories
utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are
less than the typical access time of the memory. This means that the effective system delay introduced by the
decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications (see Application
Information).
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74AC138E
CD74AC138E
55
°Cto125°C
SOIC
M
Tube
CD74AC138M
AC138M
–55
°C to 125°C
SOIC – M
Tape and reel
CD74AC138M96
AC138M
CDIP – F
Tube
CD54AC138F3A
CD54AC138F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
CD54AC138 ...F PACKAGE
CD74AC138 ...E OR M PACKAGE
(TOP VIEW)


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