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DAC8814IBDBR Arkusz danych(PDF) 5 Page - Texas Instruments

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Numer części DAC8814IBDBR
Szczegółowy opis  Quad, Serial Input 16-Bit Multiplying Digital-to-Analog Converter
Download  27 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

DAC8814IBDBR Arkusz danych(HTML) 5 Page - Texas Instruments

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PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGNDA
IOUTA
VREFA
RFBA
MSB
RS
VDD
CS
CLK
SDI
RFBB
VREFB
IOUTB
AGNDB
AGNDD
IOUTD
VREFD
RFBD
DGND
VSS
(1)
AGNDF
LDAC
SDO
NC
(1)
RFBC
VREFC
IOUTC
AGNDC
DBPackage
(TOP VIEW)
NOTE (1):Nointernalconnection
DAC8814
SBAS338D – JANUARY 2005 – REVISED SEPTEMBER 2006
PIN DESCRIPTION
PIN
NAME
DESCRIPTION
1, 14, 15, 28
AGNDA, AGNDB, AGNDC, AGNDD DAC A, B, C, D Analog ground.
2, 13, 16, 27
IOUTA, IOUTB, IOUTC, IOUTD
DAC A, B, C, D Current output.
DAC A, B, C, D Reference voltage input terminal. Establishes DAC A, B, C, D full-scale
3, 12, 17, 26
VREFA, VREFB, VREFC, VREFD
output voltage. Can be tied to VDD.
4, 11, 18, 25
RFBA, RFBB, RFBC, RFBD
Establish voltage output for DAC A, B, C, D by connecting to external amplifier output.
5
MSB
MSB Bit set during a reset pulse (RS) or at system power-on if tied to ground or VDD.
Reset pin, active low. Input register and DAC registers are set to all zeros or half-scale
6
RS
code (8000h) determined by the voltage on the MSB pin. Register data = 8000h when
MSB = 1.
7
VDD
Positive power-supply input. Specified range of operation +2.7 V to +5.5 V.
Chip select; active low input. Disables shift register loading when high. Transfers shift
8
CS
register data to input register when CS/LDAC goes high. Does not affect LDAC operation.
9
CLK
Clock input; positive edge triggered clocks data into shift register
10
SDI
Serial data input; data loads directly into the shift register.
19
NC
Not connected; leave floating.
Serial data output; input data loads directly into shift register. Data appears at SDO, 19
20
SDO
clock pulses after input at the SDI pin.
Load DAC register strobe; level sensitive active low. Transfers all input register data to
21
LDAC
the DAC registers. Asynchronous active low input. See Table 1 for operation.
22
AGNDF
High current analog force ground.
23
VSS
No internal connection.
24
DGND
Digital ground.
5
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