CD74FCT646

BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCBS735A – JULY 2000 – REVISED JULY 2000

1

POST OFFICE BOX 655303

Power

and Circuit Design

Small-Outline (M) and Shrink Small-Outline

(SM) Packages and Standard Plastic (EN)

DIP

description

The CD74FCT646 is an octal bus transceiver with 3-state outputs. It consists of D-type flip-flops and control

circuitry, arranged for multiplexed transmission of data directly from the input bus or from the internal registers.

The device uses a small-geometry BiCMOS technology. Data on the A or B bus is clocked into the registers on

the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.

The D-type flip-flops act as internal storage registers on the low-to-high transition of either CLKAB or CLKBA.

Output-enable (OE) and DIR inputs control the transceiver functions. Data present at the high impedance output

can be stored in either register, or both; however, only one of the two buses can be enabled as outputs at any

one time. The select-control (SAB and SBA) inputs can multiplex stored and transparent (real time) data. The

direction control (DIR) determines which data bus receives data when OE is low. In the high-impedance state

(OE high), A data can be stored in one register and B data can be stored in the other register. The clocks are

not gated with the DIR and OE terminals; data at the A or B terminals can be clocked into the storage flip-flops

at any time.

The outputs are a combination of bipolar and CMOS transistors that limits the output high level to two diode

simultaneous output switching. The output configuration also enhances switching speed and is capable of

sinking 64 mA.

OE and DIR control the transceiver functions. In the transceiver mode, data present at the high-impedance port

can be stored in either or both registers.

SAB and SBA can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives

data when OE is active (low). In the isolation mode (OE high), A data can be stored in one register and/or B data

can be stored in the other register.

When an output function is disabled, the input function is still enabled and can be used to store and transmit

data. Only one of the two buses, A or B, can be driven at a time.

The CD74FCT646 is characterized for operation from 0

°C to 70°C.

Copyright

© 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EN, M, OR SM PACKAGE

(TOP VIEW)

CLKAB

SAB

DIR

A1

A2

A3

A4

A5

A6

A7

A8

GND

CLKBA

SBA

OE

B1

B2

B3

B4

B5

B6

B7

B8

1

2

3

4

5

6

7

8

9

10

11

12

24

23

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21

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19

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