CDC924

133MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3STATE OUTPUTS

SCAS607B − NOVEMBER 1998 − REVISED JULY 2005

4

POST OFFICE BOX 655303

spread spectrum clock (SSC) implementation for CDC924

Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency,

which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation

of the CPU−PLL allows to distribute the energy to many different frequencies which reduces the power peak.

A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in

Figure 1.

Highest Peak

Non-SSC

SSC

δ of fnom

fnom

∆

Figure 1. Frequency Power Spectrum With and Without the Use of SSC

The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a

“down-spread modulation”.

The peak reduction depends on the modulation scheme and modulation profile. System performance and timing

requirements are the limiting factors for actual design implementations. The implementation was driven to keep

the average clock frequency closed to its upper specification limit. The modulation amount was set to

approximately −0.5%.

In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation

signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for

CDC924 is shown in Figure 2.

5

1015

20

25

3035

40

45

Period of Modulation Signal −

µs

9.97

9.98

9.99

10

10.01

10.02

10.03

Figure 2. SSC Modulation Profile