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CDC9842DWR Arkusz danych(PDF) 5 Page - Texas Instruments |
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CDC9842DWR Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 7 page CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS SCAS546B – NOVEMBER 1995 – REVISED MAY 1996 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT After SEL1, SEL0 5 Stabilization time† After OE ↑ 5 ms After power up 5 † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable. switching characteristics (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.135 V to 3.6 V, TA = 0°C to 70°C UNIT () () MIN MAX t ‡ HCLKn 200 ps tskew‡ PCLKn 400 ps Offset‡ HCLKn PCLKn 1 4 ns Jitter‡ HCKLn ±250 ps Jitter‡ PCLKn ±350 ps Duty cycle Any output 45% 55% SEL0 = L, SEL1 = L 20 ns HCKLn SEL0 = L, SEL1 = H 16.7 ns t ‡ SEL0 = H, SEL1 = L 15 ns tc‡ SEL0 = L, SEL1 = L 40 ns PCLKn SEL0 = L, SEL1 = H 33.3 ns SEL0 = H, SEL1 = L 30 ns t ‡§ HCLKn 2 ns tr‡§ PCKLn 2 ns t ‡§ HCKLn 2 ns tf‡§ PCLKn 2 ns ‡ Specifications are applicable only after the PLL stabilization time has elapsed. § Rise and fall times are characterized using the load circuits shown in Figure 1. |
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