CDCM1802RGTT datasheet(6/30 Pages) TI1

Numer części	CDCM1802RGTT

Szczegółowy opis	CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

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Producent	TI1 [Texas Instruments]

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CDCM1802

SCAS759B – APRIL 2004 – REVISED NOVEMBER 2015

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6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVPECL OUTPUT DRIVER Y0, Y0

Crossing point-to-crossing point

tDuty

Output duty cycle distortion(1)

−50

50

ps

distortion

tsk(pp)

Part-to-part skew

Any Y0 (see Note A in Figure 7)

50

ps

20% to 80% of VOUTPP

tr/tf

Rise and fall time

200

350

ps

(see Figure 8)

LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER

tpd(lh)

Propagation delay rising edge

VOX to VOX

320

600

ps

tpd(hl)

Propagation delay falling edge

VOX to VOX

320

600

ps

LVPECL pulse skew

tsk(p)

VOX to VOX

100

ps

(see Note B in Figure 7)

LVCMOS OUTPUT PARAMETER, Y1

Output skew between the LVCMOS

tskLVCMOS(o)

VOX to VDD / 2 (see Figure 7)

1.6

ns

output Y1 and LVPECL output Y0

tDuty

Output duty cycle distortion(2)

Measured at VDD / 2

−150

150

ps

tsk(pp)

Part-to-part skew

Y1 (see Note A in Figure 7)

300

ps

Propagation delay rising edge from

tpd(lh)

VOX to VDD / 2 load (see Figure 9)

1.6

2.6

ns

IN to Y1

Propagation delay falling edge from

tpd(hl)

VOX to VDD / 2 load (see Figure 9)

1.6

2.6

ns

IN to Y1

20% to 80% of swing

tr

Output rise slew rate

1.4

2.3

V/ns

(see Figure 9)

80% to 20% of swing

tf

Output fall slew rate

1.4

2.3

V/ns

(see Figure 9)

(1)

For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal.

(2)

For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal.

6.7 Jitter Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

12 kHz to 20 MHz, fout = 250 MHz to 800 MHz,

0.15

ps rms

Additive phase jitter from input to

divide by 1 mode

tjitterLVPECL

LVPECL output Y0

50 kHz to 40 MHz, fout = 250 MHz to 800 MHz,

(see Figure 1)

0.25

ps rms

divide by 1 mode

12 kHz to 20 MHz, fout = 250 MHz, divide by 1

0.25

ps rms

Additive phase jitter from input to

mode

tjitterLVCMOS

LVCMOS output Y1

50 kHz to 40 MHz, fout = 250 MHz, divide by 1

(see Figure 2)

0.4

ps rms

mode

6.8 Supply Current Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All outputs enabled and terminated with 50

Ω to VDD − 2 V on

LVPECL outputs and 10 pF on LVCMOS output,

Full load

100

mA

f = 800 MHz for LVPECL outputs and 200 MHz for LVCMOS,

IDD

Supply current

VDD = 3.3 V

Outputs enabled, no output load, f = 800 MHz for LVPECL outputs

No load

85

mA

and 200 MHz for LVCMOS, VDD = 3.6 V

IDDZ

Supply current, 3-state

All outputs 3-state by control logic, f = 0 Hz, VDD = 3.6 V

0.5

mA

6

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