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CDCVF2510PWRG4 Arkusz danych(PDF) 3 Page - Texas Instruments

Numer części CDCVF2510PWRG4
Szczegółowy opis  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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ABSOLUTE MAXIMUM RATINGS
CDCVF2510
SCAS638C – JULY 2001 – REVISED APRIL 2006
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clock input. CLK provides the clock signal to be distributed by the CDCVF2510 clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals.
CLK
24
I
CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit
is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to
phase lock the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBIN
13
I
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
G
11
I
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the
same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
FBOUT
12
O
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-
Ω series-damping resistor.
3, 4, 5, 8, 9,
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
1Y (0:9)
15, 16, 17, 20,
O
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
21
Each output has an integrated 25-
Ω series-damping resistor.
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
AVCC
23
Power
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
2, 10, 14, 22
Power
Power supply
GND
6, 7, 18, 19
Ground Ground
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
AVCC(2)
Supply voltage range
AVCC < VCC +0.7 V
VCC
Supply voltage range
-0.5 V to 4.3 V
VI(3)
Input voltage range
-0.5 V to 4.6 V
VO(4)
Voltage range applied to any output in the high or low state
-0.5 V to VCC + 0.5 V
IIK(VI < 0)
Input clamp current
-50 mA
IOK(VO < 0 or VO > VCC)
Output clamp current
±50 mA
IO(VO = 0 to VCC)
Continuous output current
±50 mA
VCC or GND
Continuous current through each
±100 mA
TA = 55°C (in still air)(5)
Maximum power dissipation
0.7 W
Tstg
Storage temperature range
-65°C to 150°C
(1)
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
AVCC must not exceed VCC + 0.7 V.
(3)
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4)
This value is limited to 4.6 V maximum.
(5)
The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For
more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book
(SCBD002).
3
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