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ADS1243IPWT Arkusz danych(PDF) 6 Page - Texas Instruments |
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ADS1243IPWT Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 25 page ADS1242, 1243 6 SBAS235B www.ti.com SPEC DESCRIPTION MIN MAX UNITS t1 SCLK Period 4tOSC Periods 3 DRDY Periods t2 SCLK Pulse Width, HIGH and LOW 200 ns t3 CS low to first SCLK Edge; Setup Time(2) 0ns t4 DIN Valid to SCLK Edge; Setup Time 50 ns t5 Valid DIN to SCLK Edge; Hold Time 50 ns t6 Delay between last SCLK edge for DIN and first SCLK edge for DOUT: RDATA, RDATAC, RREG, WREG 50 tOSC Periods t7(1) SCLK Edge to Valid New DOUT 50 ns t8(1) SCLK Edge to DOUT, Hold Time 0 ns t9 Last SCLK Edge to DOUT Tri-State 6 10 tOSC Periods NOTE: DOUT goes tri-state immediately when CS goes HIGH. t10 CS LOW time after final SCLK edge. 0 ns t11 Final SCLK edge of one command until first edge SCLK of next command: RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC 4tOSC Periods SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 2 DRDY Periods SELFCAL 4 DRDY Periods RESET (also SCLK Reset) 16 tOSC Periods t16 Pulse Width 4tOSC Periods t17 Allowed analog input change for next valid conversion. 5000 tOSC Periods t18 DOR update, DOR data not valid. 4 tOSC Periods t19 First SCLK after DRDY goes LOW: RDATAC Mode 10 tOSC Periods Any other mode 0 tOSC Periods NOTES: (1) Load = 20pF 10kΩ to GND. (2) CS may be tied LOW. TIMING DIAGRAMS TIMING CHARACTERISTICS TABLES t 4 MSB (Command or Command and Data) LSB t 5 t 1 t 3 CS SCLK (POL = 0) D IN D OUT NOTE: (1) Bit order = 0. SCLK Reset Waveform t 7 MSB(1) LSB(1) t 8 t 10 t 2 t 2 t 11 t 6 t 9 t 12 t 14 t 15 t 13 t 13 SCLK ADS1242 or ADS1243 Resets On Falling Edge 300 • t OSC < t12 < 500 • tOSC t 13 : > 5 • tOSC 550 • t OSC < t14 < 750 • tOSC 1050 • t OSC < t15 < 1250 • tOSC DIAGRAM 1. DIAGRAM 2. t 17 t 18 DRDY SCLK t DATA t 16 PDWN t 19 |
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