ADUM1100AR datasheet(3/16 Pages) AD

Numer części	ADUM1100AR

Szczegółowy opis	iCoupler Digital Isolator

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REV. E

–3–

ADuM1100

ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION1

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current

IDD1(Q)

0.1

0.3

mA

VI = 0 V or VDD1

Output Supply Current

IDD2(Q)

0.005 0.04

mA

VI = 0 V or VDD1

Input Supply Current (25 Mbps)

IDD1(25)

2.0

2.8

mA

12.5 MHz Logic Signal Frequency

(See TPC 1)

Output Supply Current

2 (25 Mbps)

IDD2(25)

0.3

0.7

mA

12.5 MHz Logic Signal Frequency

(See TPC 2)

Input Supply Current (50 Mbps)

IDD1(50)

4.0

6.0

mA

25 MHz Logic Signal Frequency,

(See TPC 1)

ADuM1100BR/ADuM1100UR Only

Output Supply Current

2 (50 Mbps)

IDD2(50)

1.2

1.6

mA

25 MHz Logic Signal Frequency,

(See TPC 2)

ADuM1100BR/ADuM1100UR Only

Input Current

II

–10

+0.01 +10

µA0 ≤ VIN ≤ VDD1

Logic High Output Voltage

VOH

VDD2 – 0.1 3.3

V

IO = –20

µA, V

I = VIH

VDD2 – 0.5 3.0

V

IO = –2.5 mA, VI = VIH

Logic Low Output Voltage

VOL

0.0

0.1

V

IO = 20

µA, VI = VIL

0.04

0.1

V

IO = 400

µA, V

I = VIL

0.3

0.4

V

IO = 2.5 mA, VI = VIL

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width

3

PW

40

ns

CL = 15 pF, CMOS Signal Levels

Maximum Data Rate

4

25

Mbps

CL = 15 pF, CMOS Signal Levels

For ADuM1100BR/ADuM1100UR

Minimum Pulse Width

3

PW

10

20

ns

CL = 15 pF, CMOS Signal Levels

Maximum Data Rate

4

50

100

Mbps

CL = 15 pF, CMOS Signal Levels

For All Grades

Propagation Delay Time to

tPHL

14.5

28

ns

CL = 15 pF, CMOS Signal Levels

Logic Low Output

5, 6

(See TPC 4)

Propagation Delay Time to

tPLH

15.0

28

ns

CL = 15 pF, CMOS Signal Levels

Logic High Output

5, 6

(See TPC 4)

Pulse Width Distortion |tPLH – tPHL|

6

PWD

0.5

3

ns

CL = 15 pF, CMOS Signal Levels

Change versus Temperature

7

10

ps/

°CCL = 15 pF, CMOS Signal Levels

Propagation Delay Skew

tPSK1

15

ns

CL = 15 pF, CMOS Signal Levels

(Equal Temperature)

6, 8

Propagation Delay Skew

tPSK2

12

ns

CL = 15 pF, CMOS Signal Levels

(Equal Temperature, Supplies)

6, 8

Output Rise/Fall Time

tR, tF

3ns

CL = 15 pF, CMOS Signal Levels

Common-Mode Transient Immunity

|CML|,

25

35

kV/

µsVI =0 or VDD1, VCM = 1000 V,

at Logic Low/High Output

9

|CMH|Transient Magnitude = 800 V

Input Dynamic Power Dissipation

CPD1

47

pF

Capacitance

10

Output Dynamic Power Dissipation

CPD2

14

pF

Capacitance

10

See Notes on page 5.

Specifications subject to change without notice.

(3.0 V

≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All min/max

specifications apply over the entire recommended operation

range, unless otherwise noted. All typical specifications are at TA = 25 C, VDD1 = VDD2 = 3.3 V.)

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