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SM320F28335-EP Arkusz danych(PDF) 8 Page - Texas Instruments

Numer części SM320F28335-EP
Szczegółowy opis  Digital Signal Controller (DSC)
Download  167 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

SM320F28335-EP Arkusz danych(HTML) 8 Page - Texas Instruments

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SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
6-10
Reset (XRS) Timing Requirements
.......................................................................................... 112
6-11
General-Purpose Output Switching Characteristics
........................................................................ 113
6-12
General-Purpose Input Timing Requirements
.............................................................................. 114
6-13
IDLE Mode Timing Requirements
........................................................................................... 116
6-14
IDLE Mode Switching Characteristics
....................................................................................... 116
6-15
STANDBY Mode Timing Requirements
..................................................................................... 116
6-16
STANDBY Mode Switching Characteristics
................................................................................ 117
6-17
HALT Mode Timing Requirements
........................................................................................... 118
6-18
HALT Mode Switching Characteristics
...................................................................................... 118
6-19
ePWM Timing Requirements
................................................................................................. 120
6-20
ePWM Switching Characteristics
............................................................................................ 120
6-21
Trip-Zone input Timing Requirements
....................................................................................... 120
6-22
High Resolution PWM Characteristics at SYSCLKOUT = (60 - 150 MHz)
.............................................. 121
6-23
Enhanced Capture (eCAP) Timing Requirement
.......................................................................... 121
6-24
eCAP Switching Characteristics
............................................................................................. 121
6-25
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
.................................................. 121
6-26
eQEP Switching Characteristics
............................................................................................. 121
6-27
External ADC Start-of-Conversion Switching Characteristics
............................................................. 121
6-28
External Interrupt Timing Requirements
.................................................................................... 122
6-29
External Interrupt Switching Characteristics
................................................................................ 122
6-30
I2C Timing
...................................................................................................................... 123
6-31
SPI Master Mode External Timing (Clock Phase = 0)
.................................................................... 124
6-32
SPI Master Mode External Timing (Clock Phase = 1)
.................................................................... 126
6-33
SPI Slave Mode External Timing (Clock Phase = 0)
...................................................................... 127
6-34
SPI Slave Mode External Timing (Clock Phase = 1)
...................................................................... 129
6-35
Relationship Between Parameters Configured in XTIMING and Duration of Pulse
................................... 130
6-36
XINTF Clock Configurations
................................................................................................... 133
6-37
External Interface Read Timing Requirements
............................................................................. 134
6-38
External Interface Read Switching Characteristics
......................................................................... 134
6-39
External Interface Write Switching Characteristics
......................................................................... 135
6-40
External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
................................... 137
6-41
External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
....................................... 137
6-42
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
....................................... 137
6-43
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
....................................... 137
6-44
External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
................................... 140
6-45
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
....................................... 140
6-46
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
...................................... 140
6-47
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
...................................................... 143
6-48
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
................................................. 144
6-49
ADC Electrical Characteristics (over recommended operating conditions)
............................................ 146
6-50
ADC Power-Up Delays
......................................................................................................... 147
6-51
Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
.............................. 147
6-52
Sequential Sampling Mode Timing
........................................................................................... 149
6-53
Simultaneous Sampling Mode Timing
....................................................................................... 150
6-54
McBSP Timing Requirements
................................................................................................ 152
6-55
McBSP Switching Characteristics
........................................................................................... 152
6-56
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
................................ 154
6-57
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
............................ 154
8
List of Tables
Copyright © 2009–2012, Texas Instruments Incorporated


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