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SN74HC132NSR Arkusz danych(PDF) 1 Page - Texas Instruments

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Numer części SN74HC132NSR
Szczegółowy opis  Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs
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SN74HC132NSR Arkusz danych(HTML) 1 Page - Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
SNx4HC132 Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs
1
1 Features
1
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive up to 10 LSTTL Loads
Low Power Consumption, 20-µA Maximum ICC
Typical tpd = 14 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
Operation from Very Slow Input Transitions
Temperature-Compensated Threshold Levels
High Noise Immunity
Same Pinouts as SN74HC00
2 Applications
Electronic Points-of-Sale
Telecom Infrastructure
Network Switches
Tests and Measurements
3 Description
The SNx4HC132 device functions as a NAND gate,
but because of the Schmitt action, it has different
input threshold levels for positive and negative going
signals.
The
SNx4HC132
devices
perform
the
Boolean
function
Y = A • B or Y = A + B in positive logic.
These circuits are temperature compensated and can
be triggered from the slowest of input ramps and still
give clean jitter-free output signals.
Device Information(1)
PART NUMBER
PACKAGE
(PINS)
BODY SIZE (NOM)
SN54HC132J
CDIP (14)
19.56 mm × 6.67 mm
SN74HC132D
SOIC (14)
4.90 mm × 3.91 mm
SN74HC132N
PDIP (14)
19.30 mm × 6.35 mm
SN54HC132FK
LCCC (20)
8.89 mm × 8.89 mm
SN54HC132W
CFP (14)
9.21 mm × 5.97 mm
SN74HC132PW
TSSOP (14)
5.00 mm × 4.40 mm
SN74HC132NS
SO (14)
10.30 mm × 5.30 mm
SN74HC132DB
SSOP (14)
6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)


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