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LM2679SX-ADJ Arkusz danych(PDF) 5 Page - Texas Instruments |
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LM2679SX-ADJ Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 37 page 5 LM2679 www.ti.com SNVS026O – MARCH 2000 – REVISED JUNE 2016 Product Folder Links: LM2679 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Junction to ambient thermal resistance (no external heat sink) for the 7-lead TO-220 package mounted vertically, with ½ inch leads in a socket, or on a PCB with minimum copper area. (3) Junction to ambient thermal resistance (no external heat sink) for the 7-lead TO-220 package mounted vertically, with ½ inch leads soldered to a PCB containing approximately 4 square inches of (1 oz.) copper area surrounding the leads. (4) Junction to ambient thermal resistance for the 7-lead DDPAK mounted horizontally against a PCB area of 0.136 square inches (the same size as the DDPAK package) of 1 oz. (0.0014 in. thick) copper. (5) Junction to ambient thermal resistance for the 7-lead DDPAK mounted horizontally against a PCB area of 0.4896 square inches (3.6 times the area of the DDPAK package) of 1 oz. (0.0014 in. thick) copper. (6) Junction to ambient thermal resistance for the 7-lead DDPAK mounted horizontally against a PCB copper area of 1.0064 square inches (7.4 times the area of the DDPAK 3 package) of 1 oz. (0.0014 in. thick) copper. Additional copper area reduces thermal resistance further. (7) Junction to ambient thermal resistance for the 14-lead VSON mounted on a PCB copper area equal to the die attach paddle. (8) Junction to ambient thermal resistance for the 14-lead VSON mounted on a PCB copper area using 12 vias to a second layer of copper equal to die attach paddle. Additional copper area reduces thermal resistance further. For layout recommendations, see AN-1187 Leadless Leadfram Package (LLP). 6.4 Thermal Information THERMAL METRIC(1) LM2679 UNIT NDZ (TO-220) KTW (TO-263) NHM (VSON) 7 PINS 7 PINS 14 PINS RθJA Junction-to-ambient thermal resistance See(2) 65 — — °C/W See(3) 45 — — See(4) — 56 — See(5) — 35 — See(6) — 26 — See(7) — — 55 See(8) — — 29 RθJC(top) Junction-to-case (top) thermal resistance 2 2 — °C/W (1) All room temperature limits are 100% tested during production with TA = TJ = 25°C. All limits at temperature extremes are specified through correlation using standard Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Typical values are determined with TA = TJ = 25°C and represent the most likely norm. 6.5 Electrical Characteristics – 3.3 V Specifications apply for TA = TJ = 25°C and RADJ = 5.6 kΩ (unless otherwise noted). PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT VOUT Output voltage VIN = 8 V to 40 V, 100 mA ≤ IOUT ≤ 5 A TJ = 25°C 3.234 3.3 3.366 V TJ = –40°C to 125°C 3.201 3.399 η Efficiency VIN = 12 V, ILOAD = 5 A 82% (1) All room temperature limits are 100% tested during production with TA = TJ = 25°C. All limits at temperature extremes are specified through correlation using standard Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Typical values are determined with TA = TJ = 25°C and represent the most likely norm. 6.6 Electrical Characteristics – 5 V Specifications apply for TA = TJ = 25°C and RADJ = 5.6 kΩ (unless otherwise noted). PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT VOUT Output voltage VIN = 8 V to 40 V, 100 mA ≤ IOUT ≤ 5 A TJ = 25°C 4.9 5 5.1 V TJ = –40°C to 125°C 4.85 5.15 η Efficiency VIN = 12 V, ILOAD = 5 A 84% |
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