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2 / 23 page LM3466 SNOSB96F – JUNE 2011 – REVISED NOVEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. MIN MAX UNIT VIN, ILED to GND –0.3 75 V COMM to GND –0.3 7 V SEN, SRC, VEQ to GND –0.3 5 V ESD Rating (2), Human Body Model –2 2 kV Storage Temperature Range –65 150 °C Junction Temperature (TJ) 150 °C (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. (2) The human body model is a 100-pF capacitor discharged through a 1.5-k Ω resistor into each pin. RECOMMENDED OPERATING CONDITIONS (1) MIN MAX UNIT Supply Voltage Range (VIN) 6 70 V Junction Temperature Range (TJ) −40 125 °C (1) Recommended Operating conditions are those under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics table. THERMAL INFORMATION SO PowerPAD TO-220 THERMAL METRIC DDA NEC(1) UNITS 8 PINS 7 PINS θJA Junction-to-ambient thermal resistance(2) 50.7 32.2 θJCtop Junction-to-case (top) thermal resistance(3) 56.1 36.4 θJB Junction-to-board thermal resistance(4) 28.9 25.2 °C/W ψJT Junction-to-top characterization parameter(5) 9.8 6.2 ψJB Junction-to-board characterization parameter(6) 28.8 23.8 θJCbot Junction-to-case (bottom) thermal resistance(7) 3.3 0.3 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM3466 |
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