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SN74ACT573N Arkusz danych(PDF) 1 Page - Texas Instruments |
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SN74ACT573N Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 22 page SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 4.5-V to 5.5-V V CC Operation D Inputs Accept Voltages to 5.5 V D Max t pd of 9.5 ns at 5 V D Inputs Are TTL-Voltage Compatible description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74ACT573N SN74ACT573N SOIC DW Tube SN74ACT573DW ACT573 40 °Cto85°C SOIC − DW Tape and reel SN74ACT573DWR ACT573 −40 °C to 85°C SOP − NS Tape and reel SN74ACT573NSR ACT573 SSOP − DB Tape and reel SN74ACT573DBR AD573 TSSOP − PW Tape and reel SN74ACT573PWR AD573 CDIP − J Tube SNJ54ACT573J SNJ54ACT573J −55 °C to 125°C CFP − W Tube SNJ54ACT573W SNJ54ACT573W 55 C to 125 C LCCC − FK Tube SNJ54ACT573FK SNJ54ACT573FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright © 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1D 2D 3D 4D 5D 6D 7D 8D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE SN54ACT573 ...J OR W PACKAGE SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 32 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2Q 3Q 4Q 5Q 6Q 3D 4D 5D 6D 7D SN54ACT573 . . . FK PACKAGE (TOP VIEW) On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. |
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Podobny opis - SN74ACT573N |
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