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SN74AHCT595PWR Arkusz danych(PDF) 9 Page - Texas Instruments |
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SN74AHCT595PWR Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 25 page 3D C3 1D C1 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 13 12 10 11 14 15 1 2 3 4 5 6 7 9 QA QB QC QD QE QF QG QH QH′ OE SRCLR RCLK SRCLK SER Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q SN54AHCT595, SN74AHCT595 www.ti.com SCLS374N – MAY 1997 – REVISED JULY 2014 9 Detailed Description 9.1 Overview The SNx4AHCT595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. 9.2 Functional Block Diagram Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN54AHCT595 SN74AHCT595 |
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