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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TDC1000-Q1 Arkusz danych(PDF) 8 Page - Texas Instruments |
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TDC1000-Q1 Arkusz danych(HTML) 8 Page - Texas Instruments |
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8 / 60 page  t7 t8 t3 t2 t1 t4 t5 t6 D15 D0 D14 SCLK CSB Prior D15 t9 Prior D1 Prior D0 90% 10% tr 90% 10% tf TDC1000, TDC1000-Q1 SNAS648B – OCTOBER 2014 – REVISED AUGUST 2015 www.ti.com 6.6 Timing Requirements TA = 25°C, VDD = VIO = 3.7 V and ƒSCLK = 1 MHz (unless otherwise noted). MIN TYP MAX UNIT ƒSCLK Serial clock frequency 26 MHz t1 High period, SCLK 16 ns t2 Low period, SCLK 16 ns t3 Set-up time, nCS to SCLK 10 ns t4 Set-up time, SDI to SCLK 12 ns t5 Hold time, SCLK to SDI 12 ns t6 SCLK transition to SDO valid time 16 ns Hold time, SCLK transition to nCS rising t7 10 ns edge t8 nCS inactive 17 ns Hold time, SCLK transition to nCS falling t9 10 ns edge tr / tf Signal rise and fall times(1) 1.8 ns (1) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates. Figure 1. SPI Timing Diagram 6.7 Switching Characteristics TA = 25°C, VDD = VIO = 3.7 V, ƒCLKIN = 8 MHz. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT START, STOP, ENABLE, CHSEL, RESET, CLOCKIN, TRIGGER, ERR TX_FREQ_DIV = 2h, NUM_TX = 1 1 μs PWSTART Pulse width for START signal TX_FREQ_DIV = 2h, NUM_TX = 2 2 μs TX_FREQ_DIV = 2h, NUM_TX ≥ 3 3 μs tr / tf Rise/fall time for START 20% to 80%, 20-pF load 0.25 ns START signal tr / tf STOP Rise/fall time for STOP signal 20% to 80%, 20-pF load 0.25 ns Maximum CLKIN input ƒCLKIN 16 MHz frequency tr / tf CLKIN CLKIN input rise/fall time (1) 20% to 80% 10 ns TRIGGER input rise/fall tr / tf TRIG 20% to 80% 10 ns time(1) tEN_TRIG Enable to trigger wait time(1) 50 ns TX_FREQ_DIV = 2h (see TX/RX Measurement tRES_TRIG Reset to trigger wait time (1) 3.05 μs Sequencing and Timing) (1) Specified by design. 8 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TDC1000 TDC1000-Q1 |
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