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TL16PNP550A Arkusz danych(PDF) 10 Page - Texas Instruments |
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TL16PNP550A Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 40 page TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUGANDPLAY (PnP) AND AUTOFLOW CONTROL SLLS190B − MARCH 1995 − REVISED MARCH 1996 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH‡ High-level output voltage IOH = − 12 mA VCC−0.8 V VOL‡ Low-level output voltage IOL = 24 mA 0.5 V VOH High-level output voltage IOH = − 4 mA (see Note 2), VCC = 0.8 V VCC−0.8 V VOL Low-level output voltage IOL = 4 mA (see Note 2) 0.5 V Il Input current VCC = 5.25 V, VSS = 0, ±1 A Il Input current VCC = 5.25 V, VI = 0 to 5.25 V, VSS = 0, All other terminals floating ±1 µA High-impedance-state output cur- VCC = 5.25 V, VSS = 0, IOZ High-impedance-state output cur- rent VCC = 5.25 V, VSS = 0, VO = 0 to 5.25 V, ±10 µA IOZ rent VO = 0 to 5.25 V, Pullup and pulldown circuits are off ±10 µA VCC = 5.25 V, TA = 25°C, SIN, DSR, DCD, CTS, and RI at 2 V, VCC = 5.25 V, TA = 25 C, SIN, DSR, DCD, CTS, and RI at 2 V, All other inputs at 0.8 V, ICC Supply current SIN, DSR, DCD, CTS, and RI at 2 V, All other inputs at 0.8 V, Clock at 4 MHz (no crystal used), 5mA ICC Supply current Clock at 4 MHz (no crystal used), No load on outputs, 5 mA No load on outputs, Baud rate = 50 kbit/s Ci(CLK) Clock input capacitance V = 0, V = 0, 15 20 pF Co(CLK) Clock output capacitance VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, 20 30 pF Ci Input capacitance CC SS f = 1 MHz, TA = 25°C, All other terminals grounded 6 10 pF Co Output capacitance All other terminals grounded 10 20 pF f(XIN−XOUT) Oscillator speed (XIN and XOUT) 16 22 MHz † All typical values are at VCC = 5 V and TA = 25°C. ‡ These parameters apply only for IRQx and D7 −D0. NOTE 2: These parameters apply for all outputs except XOUT, IRQx, and D7 − D0. clock timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALTERNATE SYMBOLS TEST CONDITIONS MIN MAX UNIT td1 Delay time, chip select (CS) high to clock (SCLK) high tSHCH 50 ns td2 Input valid to clock (SCLK) high tDVCH 100 ns tpd1 Propagation delay time, clock (SCLK) high to input transition (SIO) tCHDX 100 ns tpd2 Propagation delay time, clock (SCLK) high to output valid (SIO) tCHQV 500 ns tpd3 Propagation delay time, clock (SCLK) low to chip select transition (CS) tCLSL See Figure 18 and Figure 19 2 clock periods td3 Delay time, chip select (CS) low to output Hi-Z (SIO) tSLQZ and Figure 19 100 ns tw(SCLKH) Pulse duration, clock (SCLK) high to clock (SCLK) low (see Note 3) tCHCL 250 ns tw(SCLKL) Pulse duration, clock (SCLK) low to clock (SCLK) high (see Note 3) tCLCH 250 ns fclock Clock frequency (SCLK) (see Note 4) FCLK 0.5 0.68 MHz NOTES: 3. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles according to the ST93C56 specification. 4. The SCLK signal is attained by internally frequency dividing the XIN signal by 32. |
Podobny numer części - TL16PNP550A_08 |
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Podobny opis - TL16PNP550A_08 |
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