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TL2550RQ Arkusz danych(PDF) 3 Page - Texas Instruments |
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TL2550RQ Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 38 page Crystal OSC Buffer Data Bus Interface A2 − A0 D7 − D0 CSA CSB IOR IOW INTA INTB TXRDYA TXRDYB RXRDYA RXRDYB RESET XTAL1 XTAL2 BAUD Rate Gen 16 Byte Tx FIFO 16 Byte Rx FIFO Tx Rx UART Channel A BAUD Rate Gen 16 Byte Tx FIFO 16 Byte Rx FIFO Tx Rx UART Channel B CTSA OPA, DTRA DSRA, RIA, CDA RTSA CTSB OPB, DTRB DSRB, RIB, CDB RTSB VCC GND TXA RXA TXB RXB UART Regs UART Regs TL16C2550-Q1 www.ti.com SLWS232 – DECEMBER 2011 TL16C2550 Block Diagram DEVICE INFORMATION PIN FUNCTIONS PIN I/O DESCRIPTION NAME PFB NO. A0 28 I Address 0 select bit. Internal registers address selection A1 27 I Address 1 select bit. Internal registers address selection A2 26 I Address 2 select bit. Internal registers address selection Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low CDA, CDB 40, 16 I on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Chip select A and B (active low). These pins enable data transfers between the user CPU and the CSA, CSB 10, 11 I TL16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a low on the respective CSA and CSB pins. Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the CTSA, CTSB 38, 23 I 2550. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or D0-D4 44 -48 I/O from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive D5-D7 1 -3 serial data stream. Data set ready (active low). These inputs are associated with individual UART channels A and B. A DSRA, DSRB 39, 20 I logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR). Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s) :TL16C2550-Q1 |
Podobny numer części - TL2550RQ |
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Podobny opis - TL2550RQ |
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