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TL1454A Arkusz danych(PDF) 6 Page - Texas Instruments |
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TL1454A Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 25 page TL1454A, TL1454AY DUALCHANNEL PULSEWIDTHMODULATION (PWM) CONTROL CIRCUIT SLVS423 A− MAY 2002 − REVISED SEPTEMBER 2002 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dead-time control (DTC) and soft start The two PWM channels have independent dead-time control inputs so that the maximum power-switch duty cycles can be limited to less then 100%. The dead-time is set with a voltage applied to DTC; the voltage is typically obtained from a resistive divider connected between the reference and ground as shown in Figure 4. Soft start is implemented by adding a capacitor between REF and DTC. The voltage, VDT, required to limit the duty cycle to a maximum value is given by: V DT + V O(max) * D V O(max) * V O(min) * 0.65 where VO(max) and VO(min) are obtained from Figure 9, and D is the maximum duty cycle. Predicting the regulator startup or rise time is complicated because it depends on many variables, including: input voltage, output voltage, filter values, converter topology, and operating frequency. In general, the output will be in regulation within two time constants of the soft-start circuit. A five-to-ten millisecond time constant usually works well for low-power converters. The DTC input can be grounded in applications where achieving a 100% duty cycle is desirable, such as a buck converter with a very low input-to-output differential voltage. However, grounding DTC prevents the implementation of soft start, and the output voltage overshoot at power-on is likely to be very large. A better arrangement is to omit RDT1 (see Figure 4) and choose RDT2 = 47 kΩ. This configuration ensures that the duty cycle can reach 100% and still allows the designer to implement soft start using CSS. CSS REF TL1454A RDT1 DTC RDT2 16 Figure 4. Dead-Time Control and Soft Start PWM comparator Each of the PWM comparators has dual inverting inputs. One inverting input is connected to the output of the error amplifier; the other inverting input is connected to the DTC terminal. Under normal operating conditions, when either the error-amplifier output or the dead-time control voltage is higher than that for the PWM triangle wave, the output stage is set inactive (OUT1 low and OUT2 high), turning the external power stage off. undervoltage-lockout (UVLO) protection The undervoltage-lockout circuit turns the output circuit off and resets the SCP latch whenever the supply voltage drops too low (to approximately 2.9 V) for proper operation. A hysteresis voltage of 200 mV eliminates false triggering on noise and chattering. short-circuit protection (SCP) The TL1454A SCP function prevents damage to the power switches when the converter output is shorted to ground. In normal operation, SCP comparator 1 clamps SCP to approximately 185 mV. When one of the converter outputs is shorted, the error amplifier output (COMP) will be driven below 1 V to maximize duty cycle and force the converter output back up. When the error amplifier output drops below 1 V, SCP comparator 1 releases SCP, and capacitor, CSCP, which is connected between SCP and GND, begins charging. If the error-amplifier output rises above 1 V before CSCP is charged to 1 V, SCP comparator 1 discharges CSCP and normal operation resumes. If CSCP reaches 1 V, SCP comparator 2 turns on and sets the SCP latch, which turns off the output drives and resets the soft-start circuit. The latch remains set until the supply voltage is lowered to 2 V or less, or CSCP is discharged externally. |
Podobny numer części - TL1454A |
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Podobny opis - TL1454A |
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