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TDA2LFBTQABCQ1 Arkusz danych(PDF) 4 Page - Texas Instruments |
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TDA2LFBTQABCQ1 Arkusz danych(HTML) 4 Page - Texas Instruments |
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4 / 426 page  4 TDA2SX, TDA2SG TDA2HG, TDA2HV, TDA2LF SPRS951A – DECEMBER 2015 – REVISED APRIL 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2HG TDA2HV TDA2LF Table of Contents Copyright © 2015–2016, Texas Instruments Incorporated Table of Contents 1 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 1.4 Related Links ......................................... 2 1.5 Functional Block Diagram ........................... 2 2 Revision History ......................................... 5 3 Device Comparison ..................................... 6 3.1 Device Comparison Table ............................ 6 3.2 Related Products ..................................... 8 4 Terminal Configuration and Functions .............. 9 4.1 Terminal Assignment ................................. 9 4.2 Ball Characteristics .................................. 10 4.3 Multiplexing Characteristics ......................... 77 4.4 Signal Descriptions .................................. 95 5 Specifications ......................................... 136 5.1 Absolute Maximum Ratings ........................ 136 5.2 ESD Ratings ....................................... 137 5.3 Power on Hour (POH) Limits ...................... 137 5.4 Recommended Operating Conditions ............. 138 5.5 Operating Performance Points ..................... 141 5.6 Power Consumption Summary .................... 158 5.7 Electrical Characteristics ........................... 158 5.8 Thermal Resistance Characteristics ............... 166 5.9 Power Supply Sequences ......................... 167 6 Clock Specifications ................................. 178 6.1 Input Clock Specifications ......................... 179 6.2 DPLLs, DLLs Specifications ....................... 187 7 Timing Requirements and Switching Characteristics ........................................ 191 7.1 Timing Test Conditions ............................ 191 7.2 Interface Clock Specifications ..................... 191 7.3 Timing Parameters and Information ............... 191 7.4 Recommended Clock and Control Signal Transition Behavior ............................................ 193 7.5 Virtual and Manual I/O Timing Modes ............. 193 7.6 Video Input Ports (VIP) ............................ 196 7.7 Display Subsystem – Video Output Ports ......... 214 7.8 Display Subsystem – High-Definition Multimedia Interface (HDMI) ................................... 225 7.9 External Memory Interface (EMIF) ................. 225 7.10 General-Purpose Memory Controller (GPMC) ..... 225 7.11 Timers .............................................. 247 7.12 Inter-Integrated Circuit Interface (I2C) ............. 248 7.13 Universal Asynchronous Receiver Transmitter (UART) ............................................. 251 7.14 Multichannel Serial Peripheral Interface (MCSPI) . 252 7.15 Quad Serial Peripheral Interface (QSPI) .......... 258 7.16 Multichannel Audio Serial Port (McASP) .......... 264 7.17 Universal Serial Bus (USB) ........................ 284 7.18 Serial Advanced Technology Attachment (SATA) . 286 7.19 Peripheral Component Interconnect Express (PCIe) .............................................. 286 7.20 Controller Area Network Interface (DCAN) ........ 287 7.21 Ethernet Interface (GMAC_SW) ................... 288 7.22 eMMC/SD/SDIO ................................... 298 7.23 General-Purpose Interface (GPIO) ................ 325 7.24 System and Miscellaneous interfaces ............. 325 7.25 Test Interfaces ..................................... 325 8 Applications, Implementation, and Layout ...... 330 8.1 Introduction ........................................ 330 8.2 Power Optimizations ............................... 331 8.3 Core Power Domains .............................. 345 8.4 Single-Ended Interfaces ........................... 356 8.5 Differential Interfaces .............................. 358 8.6 Clock Routing Guidelines .......................... 379 8.7 DDR2/DDR3 Board Design and Layout Guidelines .......................................... 381 9 Device and Documentation Support .............. 416 9.1 Device Nomenclature & Orderable Information .... 416 9.2 Tools and Software ................................ 418 9.3 Documentation Support ............................ 419 9.4 Receiving Notification of Documentation Updates . 419 9.5 Related Links ...................................... 419 9.6 Community Resources ............................. 420 9.7 Trademarks ........................................ 420 9.8 Electrostatic Discharge Caution ................... 420 9.9 Export Control Notice .............................. 420 9.10 Glossary ............................................ 421 10 Mechanical Packaging and Orderable Information ............................................. 422 10.1 Mechanical Data ................................... 422 |
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