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SL5162KGMP1S Arkusz danych(PDF) 2 Page - Zarlink Semiconductor Inc |
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SL5162KGMP1S Arkusz danych(HTML) 2 Page - Zarlink Semiconductor Inc |
2 / 10 page SL5162 Multistandard VHF and UHF Television Demodulator Supersedes September 1996 edition, DS4497-2.1 DS4497-3.0 September 1998 The SL5162 multistandard modulator up-converts a baseband video signal with separate audio frequency input on to a VHF or UHF carrier up to 860MHz. It provides RF signals with negative or positive video modulation and AM or FM sound subcarrier to satisfy both PAL/NTSC and SECAM applications. The on-chip local oscillator uses an external resonator tank which may be controlled via any Mitel 1.3GHz synthesiser. Selection of both video and sound standards are provided by level switching of a single pin. A video AGC circuit is provided to ensure constant modulation depth. In PAL mode this may be disabled and a white clip circuit switched in to prevent overmodulation if desired. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RF1 RF2 VCC2 LOIN1 LOOP1 LOOP2 LOIN2 VEE2 ST1 ST2 AGC VIDEO TSG VEE1 OP2 OP1 MSS SUB2 VCC1 AUDIO SL5162 MP20 Figure 1 Pin connections – top view FEATURES s Covers both Negative and Positive Modulation Sys- tems s Internal AGC with Disable s Control of Sound and Video Standard via Single Pin s Symmetrical 75 ΩRF Outputs for Low Radiation s Audio Input with AM/FM Sound Modulator s Switchable Video Test Signal Generator (TSG) s Intercarrier Input for Second Sound Channel s ESD Protection 2 55 °C to1150°C 2 20 °C to1150°C 2 10 °C to180°C 2 0·3V to17·0 V 2 0·3V to17·0V ABSOLUTE MAXIMUM RATINGS Storage temperature Junction temperature Ambient temperature Supply Voltage Voltage at any other pin ORDERING INFORMATION SL5162/KG/MP1S Miniature plastic package SL5162/KG/MP1T Tape and reel MIXER DRIVER FM/AM SELECT OFFSET ADJUST UHF MIXER AUDIO OSC FM AGC AGC CLIP CLAMP 75 VIDEO INPUT UHF OSC 5 6 4 7 13 19 20 UHF TANK SUBCARRIER 2 12 PRESCALER OUTPUTS 15 16 MODULATED OUTPUTS 9 10 SOUND TANK 11 AUDIO INPUT 14 MODE SELECT TSG ENABLE CLIP LOGIC TSG 18 Figure 2 Block diagram |
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