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74LVC2GU04GV Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74LVC2GU04GV Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 15 page 2004 Sep 21 2 Philips Semiconductors Product specification Dual inverter 74LVC2GU04 FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • 5 V tolerant input/output for interfacing with 5 V logic • High noise immunity • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. •±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • Multiple package options • Specified from −40 °C to +85 °C and −40 °C to +125 °C. DESCRIPTION The 74LVC2GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. The 74LVC2GU04 provides two inverters. Each inverter is a single stage with unbuffered output. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay input nA to output nY VCC = 1.8 V; CL = 30 pF; RL =1kΩ 2.3 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 1.8 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.6 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.3 ns VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.7 ns CI input capacitance 5 pF CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 7.8 pF |
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