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RTL8139C Arkusz danych(PDF) 6 Page - List of Unclassifed Manufacturers |
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RTL8139C Arkusz danych(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 62 page RTL8139C(L) 2002/01/10 Rev.1.4 6 5. Pin Descriptions In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation. 5.1 Power Management/Isolation Interface Symbol Type Pin No Description PMEB (PME#) O/D 76 Power Management Event: Open drain, active low. Used by the RTL8139C(L) to request a change in its current power management state and/or to indicate that a power management event has occurred. ISOLATEB (ISOLATE#) I 95 Isolate Pin: Active low. Used to isolate the RTL8139C(L) from the PCI bus. The RTL8139C(L) does not drive its PCI outputs (excluding PME#) and does not sample its PCI input (including RST# and PCICLK) as long as the Isolate pin is asserted. LWAKE/ CSTSCHG O 83 LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3): This signal is used to inform the motherboard to execute the wake-up process. The motherboard must support Wake-On-LAN (WOL). There are 4 choices of output, including active high, active low, positive pulse, and negative pulse, that may be asserted from the LWAKE pin. Please refer to the LWACT bit in the CONFIG1 register and the LWPTN bit in the CONFIG4 register for the setting of this output signal. The default output is an active high signal. Once a PME event is received, the LWAKE and PMEB assert at the same time when the LWPME (bit4, CONFIG4) is set to 0. If the LWPME is set to 1, the LWAKE asserts only when the PMEB asserts and the ISOLATEB is low. CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal is used in CardBus applications only and is used to inform the motherboard to execute the wake-up process whenever a PME event occurs. This is always an active high signal, and the setting of LWACT (bit 4, Config1), LWPTN (bit2, Config4), and LWPME (bit4, Config4) mean nothing in this case. This pin is a 3.3V signaling output pin. 5.2 PCI Interface Symbol Type Pin No Description AD31-0 T/S 120-123, 125-128, 4-6, 8-11, 13, 26-29, 31-34, 37-39, 41-45 PCI address and data multiplexed pins. C/BE3-0 T/S 2, 14, 24, 36 PCI bus command and byte enables multiplexed pins. CLK I 116 Clock: This PCI Bus clock provides timing for all transactions and bus phases, and is input to PCI devices. The rising edge defines the start of each phase. The clock frequency ranges from 0 to 33MHz. CLKRUNB I/O 75 Clock Run: This signal is used by the RTL8139C(L) to request starting (or speeding up) the clock, CLK. CLKRUNB also indicates the clock status. For the RTL8139C(L), CLKRUNB is an open drain output as well as an input. The RTL8139C(L) requests the central resource to start, speed up, or maintain the interface clock by the assertion of CLKRUNB. For the host system, it is an S/T/S signal. The host system (central resource) is responsible for maintaining CLKRUNB asserted, and for driving it high to the negated (deasserted) state. |
Podobny numer części - RTL8139C |
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Podobny opis - RTL8139C |
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