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TPD1E10B09DPYR Arkusz danych(PDF) 9 Page - Texas Instruments

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Numer części TPD1E10B09DPYR
Szczegółowy opis  Single-Channel ESD Protection Device in 0402 Package
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TPD1E10B09
www.ti.com
SLLSEB0D – FEBRUARY 2012 – REVISED SEPTEMBER 2015
8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer should make sure:
The voltage range on the protected line does not exceed the reverse standoff voltage of the TVS diode(s)
(VRWM).
The operating frequency is supported by the I/O capacitance, CIO, of the TVS diode.
The IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode.
For this application, the audio signal voltage range is –8 V to 8 V. The VRWM for the TVS is –9.5 V to 9.5 V;
therefore, the bidirectional TVS will not break down during normal operation, and normal operation of the audio
signal will not be affected due to the signal voltage range. In this application, a bidirectional TVS like
TPD1E10B09 is required.
Next, consider the frequency content of this audio signal. In this application with the class AB amplifier, the
frequency content is from 20 Hz to 20 kHz; ensure that the TVS I/O capacitance will not distort this signal by
filtering it. With TPD1E10B09 typical capacitance of 10 pF, which leads to a typical cutoff frequency of just under
500 MHz, this diode has sufficient bandwidth to pass the audio signal without distorting it.
Finally, the human interface in this application requires protection for ±15-kV Contact and ±15-kV Air-Gap ESD,
which is above the standard Level 4 IEC 61000-4-2 system-level ESD protection. A standard TVS cannot survive
this level of IEC ESD stress. However, TPD1E10B09 can survive at least ±20-kV Contact and ±20-kV Air-Gap
ESD. Therefore, the device can provide sufficient ESD protection for the interface, even though the requirements
are stringent. For any TVS diode to provide its full range of ESD protection capabilities, as well as to minimize
the noise and EMI disturbances the board will see during ESD events, it is crucial that a system designer uses
proper board layout of their TVS ESD protection diodes. See Layout for instructions on properly laying out
TPD1E10B09.
8.2.3 Application Curves
Figure 11. ESD Clamp Voltage +8-kV Contact ESD
Figure 12. ESD Clamp Voltage –8-kV Contact ESD
Copyright © 2012–2015, Texas Instruments Incorporated
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