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TPD4E1B06 Arkusz danych(PDF) 10 Page - Texas Instruments

Numer części TPD4E1B06
Szczegółowy opis  4-Channel Ultra Low Leakage ESD Protection Device
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Strona internetowa  http://www.ti.com
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TPD4E1B06 Arkusz danych(HTML) 10 Page - Texas Instruments

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1
D0
D1
Legend
Signal VIA
Top Layer
Bottom Layer
VIA to Ground Plane
1
D0
D1
VIA to Ground Plane
Legend
TPD4E1B06
SLVSBQ8C – DECEMBER 2012 – REVISED JULY 2014
www.ti.com
10 Layout
10.1 Layout Guidelines
Place the device as close to the connector as possible.
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
The PCB designer should minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Examples
Figure 11 shows a layout example for theTPD4E1B06DCK. Pins 1 & 2 and 4 & 5 are routed differentially. Pin 3 is
routed to the ground plane. Pin 6 does not have an internal connection in the device and does not need to be
routed anywhere on the board. It is also acceptable to connect pin 6 to the ground plane.
Figure 11. DCK Layout Example Showing Two Data Pairs, D0 and D1
Figure 12 shows a layout example for theTPD4E1B06DRL. Pins 1 & 6 and 3 & 4 are routed differentially. Pin 2 is
routed to the ground plane. Pin 5 does not have an internal connection in the device and does not need to be
routed anywhere on the board. It is also acceptable to connect pin 5 to the ground plane.
Figure 12. DRL Layout Example Showing Two Data Pairs, D0 and D1
10
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