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TPIC44H01 Arkusz danych(PDF) 11 Page - Texas Instruments

Numer części TPIC44H01
Szczegółowy opis  4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
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TPIC44H01 Arkusz danych(HTML) 11 Page - Texas Instruments

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TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
serial data operation
The TPIC44H01 offers a serial interface to a host microcontroller to receive control data and to return fault data
to the host controller. For the serial interface operation, it is assumed that all parallel inputs, IN1 – 4, are low. The
serial interface consists of:
SCLK
Serial clock
CS
Chip select (active low)
SDI
Serial data input
SDO
Serial data output
After a CS transition from high to low, serial data at the SDI pin is shifted, MSB first, into the serial input shift
register on the low-to-high transition of SCLK. Eight SCLK cycles are required (see Table 1) to shift the first data
bit from LSB to MSB of the shift register. Eight SCLK cycles must occur before a transition from low to high on
CS to insure proper control of the outputs. Less than eight clock cycles will result in fault data being latched into
the output control buffer. Sixteen bits of data can be shifted into the device, but the first eight bits shifted out are
always the fault data and the last eight bits shifted in are always the output control data. A low-to-high transition
on CS will latch bits 1 – 4 of the serial shift register into the output control buffer, bits 5 – 7 into the deglitch timer
control register, and bit 8 into the sleep state latch. A logic 0 in SDI bit1 –4 will turn the corresponding gate drive
output off (providing the parallel input for that channel is at a logic low state); likewise, a logic 1 will turn the output
on. Functionality of bits 5 – 7 is detailed in Table 4. A logic 1 in SDI bit 8 will enable sleep state and a logic 0 will
maintain normal operation.
Table 1. Serial Data Input Shift Register Bit Assignment
LSB
(Last In)
MSB
(First In)
SDI
B1
B2
B3
B4
B5
B6
B7
B8
IN1
IN2
IN3
IN4
DG1
DG2
DG3
SLEEP
Shift Direction
SDI, Normal Protocol (8–SCLKs)
Table 2. Serial Data Output Shift Register Bit Assignment
MSB
(First Out)
LSB
(Last Out)
SDO
B8
B7
B6
B5
B4
B3
B2
B1
F4B
F4A
F3B
F3A
F2B
F2A
F1B
F1A
Shift Direction
SDO, Fault Bit Protocol (8–SCLKs)
Table 3. Fault Bit Encoding
FAULT CONDITION
FxB
FxA
FLT
Normal – no faults
X
X
1
Over-voltage
0
0
0
Open-load
0
1
0
Over-current
1
0
0
Short-to-ground
1
1
0


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