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Si5346-D-EVB Arkusz danych(PDF) 6 Page - Silicon Laboratories |
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Si5346-D-EVB Arkusz danych(HTML) 6 Page - Silicon Laboratories |
6 / 55 page 3.3.5 Holdover Mode Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and delay are programmable, as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignor- ing frequency data that may be corrupt just before the input clock failure. Programmable delay Clock Failure and Entry into Holdover time 0s Historical Frequency Data Collected Programmable historical data window used to determine the final holdover value 120s 1s,10s, 30s, 60s 30ms, 60ms, 1s,10s, 30s, 60s Figure 3.2. Programmable Holdover Window When entering Holdover Mode, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Holdover Mode, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If the clock input becomes valid, a DSPLL will automatically exit the Holdover Mode and reacquire lock to the new input clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless, and its rate is controlled by the DSPLL bandwidth or the fastlock bandwidth. These options are register program- mable. Add new section The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on ramped input switching, see 3.6.6 Ramped Input Switching. Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable holdover exit BW. 3.4 Digitally-Controlled Oscillator (DCO) Mode The DSPLLs support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency step words (FSW).The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or dec- rement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The DCO mode is available when the DSPLL is operating in either Free-run or Locked Mode. Si5347/46 Rev D Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 5 |
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