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FAN5068MPX Arkusz danych(PDF) 5 Page - Fairchild Semiconductor |
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FAN5068MPX Arkusz danych(HTML) 5 Page - Fairchild Semiconductor |
5 / 18 page FAN5068 PRODUCT SPECIFICATION REV. 1.0.1 9/9/04 5 8 BOOT Boot. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC contains a boot diode to VCC. 9 HDRV High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. 10 SW Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. 11 ISNS Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. 12 LDRV Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. 13 PGOOD Power Good Flag. An open-drain output that will pull LOW when FB is outside of a ±10% range of the 0.9V reference and the LDO outputs are > 80% or < 110% of its reference. PGOOD goes low when S3 is high. The power good signal from the PWM regulator enables the VTT regulator and the LDO controller. 14 VCC VCC. The IC takes its bias power from this pin. Also used for gate drive power. The IC is held in standby until this pin is above 4.35V (UVLO threshold). 15 3.3 ALW 3.3V LDO Output. Internal LDO output. Turned off in S0, on in S5 or S3 modes. 16 S3#O S3# Output. Open-drain output which pulls the gates of two N-Channel blocking MOSFETs low in S5 and S3. This pin goes high (open) in S0 mode. 17 S3#I S3 Input. When LOW, turns off the VTT and 1.2V LDO regulators and turns on the 3.3V regulator. Also causes S3#O to pull low to turn off blocking switch Q3 as shown in Figure 1. PGOOD is low when S3#I is LOW. 18 EN ENABLE. Typically tied to S5#. When this pin is low, the IC is in a low quiescent current state, all regulators are off and S3#O is low. 19 GND GROUND for the IC are tied to this pin and also connected to P1. 20 ILIM Current Limit. A resistor from this pin to GND sets the current limit. 21 SS Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization as well as sets the initial slew rate of the LDO controllers when transitioning from S3 to S0. This pin is charged/discharged with a 5µA current source during initialization, and charged with 50µA during PWM soft-start. 22 COMP Output of the PWM error amplifier. Connect compensation network between this pin and FB. 23 FB VDDQ Feedback. The feedback from PWM output. Used for regulation as well as PGOOD, under-voltage, and over-voltage protection and monitoring. 24 REF IN VTT Reference. Input which provides the reference for the VTT regulator. A precision internal divider from VDDQ IN is provided. Pin Definitions (continued) Pin # Pin Name Pin Function Description |
Podobny numer części - FAN5068MPX |
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Podobny opis - FAN5068MPX |
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