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GS82583ED18 Arkusz danych(PDF) 7 Page - GSI Technology |
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GS82583ED18 Arkusz danych(HTML) 7 Page - GSI Technology |
7 / 26 page GS82583ED18/36GK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.05 8/2016 7/26 © 2014, GSI Technology DLL Operation A DLL is implemented in these devices to control all output timing. It uses the CK input clock as a source, and is enabled when all of the following conditions are met: 1. RST is de-asserted Low, and 2. The DLL pin is asserted High, and 3. CK cycle time t KHKH (max), as specified in the AC Timing Specifications section. Once enabled, the DLL requires 64K stable clock cycles in order to lock/synchronize properly. When the DLL is enabled, it aligns output clocks and read data to input clocks, and it generates all mid-cycle output timing. See the Output Timing section for more information. The DLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the DLL to lose lock/ synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see “tKJITcc” in the AC Timing Specifications section for more information). However, the DLL must be resynchronized (i.e. disabled and then re-enabled) whenever the nominal input clock frequency is changed. The DLL is disabled when any of the following conditions are met: 1. RST is asserted High, or 2. The DLL pin is de-asserted Low, or 3. CK is stopped for at least 30ns, or CK cycle time 30ns. Clock Truth Table Previous Operation SA R W Current Operation D Q (tn–1) CK (tn) CK (tn) CK (tn) (tn) KD (tn+1) KD (tn+1½) KD (tn+2) KD (tn+2½) CQ (tn+3) CQ (tn+3½) CQ (tn+4) CQ (tn+4½) NOP X 1 1 NOP X X — — 0 / High-Z — Write X 1 X NOP D3 D4 — — 0 / High-Z — Read X X 1 NOP X X — — Q3 Q4 — NOP V 1 0 Write D1 D2 D3 D4 0 / High-Z — Read V X 0 Write D1 D2 D3 D4 Q3 Q4 — NOP V 0 X Read X X — — Q1 Q2 Q3 Q4 Write V 0 X Read D3 D4 — — Q1 Q2 Q3 Q4 Notes: 1. 1 = High; 0 = Low; V = Valid; X = don’t care. 2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of Write Data transferred during Write operations. 3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of Read Data transferred during Read operations. 4. When D ODT is enabled, Q pins are driven Low for one cycle in response to NOP and Write commands, 3 cycles after the command is sampled, except when preceded by a Read command. When D ODT is disabled, Q pins are tri-stated for one cycle in response to NOP and Write commands, 3 cycles after the command is sampled, except when preceded by a Read command. |
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