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SL811HST Arkusz danych(PDF) 4 Page - Cypress Semiconductor

Numer części SL811HST
Szczegółowy opis  Embedded USB Host/Slave Controller
Download  29 Pages
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

SL811HST Arkusz danych(HTML) 4 Page - Cypress Semiconductor

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SL811HS
Document #: 38-08008 Rev. *A
Page 4 of 29
1.0
Conventions
1,2,3,4
Numbers without annotations are decimals.
Dh, 1Fh, 39h
Hexadecimal numbers are followed by an “h.”
0101b, 010101b
Binary numbers are followed by a “b.”
bRequest, n
Words in italics indicate terms defined by USB Specification or by this Specification.
2.0
Definitions
USB
Universal Serial Bus
SL811HS
The SL811HS is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip.
This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package
(SL811HST-AC). Throughout this document, “SL811HS” refers to both packages unless otherwise
noted.
Note: This chip does not include CPU.
SL11
The SL11 is a Cypress USB Peripheral Device Controller, providing multiple functions on a single chip.
This part is offered in both a 28-pin PLCC package (SL11) and a 48-pin TQFP package (SL11T-AC).
Throughout this document, “SL11” refers to both packages unless otherwise noted.
Note: This chip does not include a CPU.
SL11H
The SL11H is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip. This
part is offered in both a 28-Pin PLCC package (SL11H) and a 48-Pin TQFP package (SL11HT-AC).
Throughout this document, “SL11H” refers to both packages unless otherwise noted.
Note: This chip does not include CPU.
LSB
Least Significant Bit
MSB
Most Significant Bit
R/W
Read/Write
PLL
Phase Lock Loop
RAM
Random Access Memory
SIE
Serial Interface Engine
ACK
Handshake packet indicates a positive acknowledgment.
NAK
Handshake packet indicating a negative acknowledgment
USBD
Universal Serial Bus Driver
SOF
Start of Frame is the first transaction in each frame. It allows endpoints to identify the start of the frame
and synchronize internal endpoint clocks to the host.
CRC
Cyclic Redundancy Check
HOST
The host computer system on which the USB Host Controller is installed
3.0
References
[Ref 1] USB Specification 1.1:
http://www.usb.org.
4.0
Introduction
4.1
Block Diagram
The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB
peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of
buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.
The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed trans-
ceivers. The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.
The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support
to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Inter-
nally, the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.
The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages
operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.


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