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STK5Q4U362J-E Arkusz danych(PDF) 8 Page - ON Semiconductor |
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8 / 15 page STK5Q4U362J-E www.onsemi.com 8 APPLICATIONS INFORMATION Input / Output Timing Chart Figure 12. Input/Output Timing Chart Notes 1. This section of the timing diagram shows the effect of cross-conduction prevention. 2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume. 3. This section shows that when the bootstrap voltage VBS drops, the corresponding high side output (U or V or W) is switched off. When VBS rises sufficiently, normal operation will resume. 4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes later after the over-current condition is removed. 5. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input before enabling the driver for the HIN signal. Input / Output Logic Table INPUT OUTPUT HIN LIN Itrip Enable High side IGBT Low side IGBT U, V, W FAULT H L L H ON (Note 5) OFF VP OFF L H L H OFF ON NU, NV, NW OFF L L L H OFF OFF High Impedance OFF H H L H OFF OFF High Impedance OFF X X H H OFF OFF High Impedance ON X X X L OFF OFF High Impedance OFF |
Podobny numer części - STK5Q4U362J-E |
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Podobny opis - STK5Q4U362J-E |
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