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KM29U128T Arkusz danych(PDF) 2 Page - Samsung semiconductor

Numer części KM29U128T
Szczegółowy opis  16M x 8 Bit NAND Flash Memory
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Producent  SAMSUNG [Samsung semiconductor]
Strona internetowa  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM29U128T Arkusz danych(HTML) 2 Page - Samsung semiconductor

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KM29U128T, KM29U128IT
FLASH MEMORY
2
16M x 8 Bit NAND Flash Memory
The KM29U128 is a 16M(16,777,216)x8bit NAND Flash Mem-
ory with a spare 512K(524,288)x8bit. Its NAND cell provides
the most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typically 200
µs and an erase operation can be performed in typ-
ically 2ms on a 16K-byte block. Data in the page can be read
out at 50ns cycle time per byte. The I/O pins serve as the ports
for address and data input/output as well as command inputs.
The on-chip write controller automates all program and erase
functions including pulse repetition, where required, and inter-
nal verify and margining of data. Even the write-intensive sys-
tems can take advantage of the KM29U128
′s extended
reliability of 1,000,000 program/erase cycles by providing either
ECC(Error Correcting Code) or real time mapping-out algo-
rithm. These algorithms have been implemented in many mass
storage applications and also the spare 16 bytes of a page
combined with the other 512 bytes can be utilized by system-
level ECC.
The KM29U128 is an optimum solution for large nonvolatile
storage applications such as solid state file storage, digital
voice recorder, digital still camera and other portable applica-
tions requiring non-volatility.
GENERAL DESCRIPTION
FEATURES
• Voltage supply : 2.7V~3.6V
• Organization
- Memory Cell Array : (16M + 512K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• 528-Byte Page Read Operation
- Random Access : 10
µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200
µs(typ.)
- Block Erase time : 2ms(typ.)
• Command/Address/Data Multiplexed I/O port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
• Command Register Operation
• Package : 48 - pin TSOP Type1 - 12 x 20 / 0.5 mm pitch
PIN CONFIGURATION
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
48-pin TSOP1
Standard Type
12mm x 20mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
SE
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Pin Name
Pin Function
I/O0 ~ I/O7
Data Input/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
SE
Spare area Enable
R/B
Ready/Busy output
VCC
Power(+2.7V~3.6V)
VSS
Ground
N.C
No Connection
PIN DESCRIPTION


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