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TSB41BA3APFP Arkusz danych(PDF) 4 Page - Texas Instruments

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Numer części TSB41BA3APFP
Szczegółowy opis  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
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Strona internetowa  http://www.ti.com
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TSB41BA3APFP Arkusz danych(HTML) 4 Page - Texas Instruments

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TSB41BA3A
SLLA224A – JUNE 2006 – REVISED OCTOBER 2006
To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0,
S1_PC1, and S0_PC2) need to be pulled to VCC or ground through a 1-k
Ω resistor. The port must be operated
in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b Beta-only connector is connected to the
port. To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly
to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only
mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode
is provided to ensure that 1394b signaling is never sent across a 1394a cable.
NOTE:
A bilingual port can only connect to a 1394b-only port that operates at S400b. It
cannot establish a connection to a S200b or S100b port. A port that has been forced
to S400b (B4) can connect to a 1394b-only port at S400b (B4) or S200b (B2) or
S100b (B1). A port that has been forced to S200b can connect to a 1394b-only port
at S200b or S100b. A port that has been forced to S100b can only connect to a
1394b-only port at S100b.
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal must be connected to V
DD through a 1-kΩ resistor. The SE and SM terminals
must be tied to ground through a 1-k
Ω resistor.
Three package terminals are used as inputs to set the default value for three configuration status bits in the
self-ID packet. They can be pulled high through a 1-k
Ω resistor or hardwired low as a function of the equipment
design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default
power–class status for the node (the need for power from the cable or the ability to supply power to the cable).
The contender bit in the PHY register set indicates that the node is a contender either for the isochronous
resource manager (IRM) or for the bus manager (BM). On the TSB41BA3A, this bit can only be set by a write to
the PHY register set. If a node is a contender for IRM or BM, then the node software must set this bit in the PHY
register set.
The LPS (link power status) terminal works with the S5_LKON terminal to manage the power usage in the node.
The LPS signal from the LLC is used with the LCtrl bit to indicate the active/power status of the LLC. The LPS
signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is
controlled solely by the LPS input regardless of the state of the LCtrl bit).
NOTE:
The TSB41BA3A does not have a cable-not-active (CNA) terminal. To achieve a
similar function, the individual PHY ports can be set up to issue interrupts whenever
the port changes state. If the LPS terminal is low, then this generates a link-on
(LKON) output clock. See register bits PIE, PEI, and WDIE along with the individual
interrupt bits.
The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal
definition) and is considered active otherwise. When the TSB41BA3A detects that the LPS input is inactive, the
PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0
state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for
more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a
low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3A continues the
necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC
interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the
PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled
state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having
entered the LPS_DISABLE time, the TSB41BA3A issues a bus reset. This broadcasts the node self-ID packet,
which contains the updated L bit state (the PHY LLC now being accessible).
4
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