ADT7490_16 datasheet(11/75 Pages) ONSEMI

Numer części	ADT7490

Szczegółowy opis	Remote Thermal Monitor and Fan Controller

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ADT7490

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the IMON value and the measured VCCP value on Pin 23, the

CPU power consumption can be calculated. See the

appropriate Analog Devices flex mode data sheet for

calculations. The IMON information can be considered as an

early indication of an increase in CPU temperature.

Startup Operation

At startup, the ADT7490 turns the fans on to 100% PWM.

This allows the most robust operation at turn-on.

Serial Bus Interface

Control of the ADT7490 is carried out using the serial

system management bus (SMBus). The ADT7490 is

connected to this bus as a slave device, under the control of

a master controller. The ADT7490 has a 7-bit serial bus

address. When the device is powered up with Pin 13

(PWM3/ADDREN) high, the ADT7490 has a default

SMBus address of 0101110 or 0x2E. The read/write bit must

be added to obtain the 8-bit address. If more than one

ADT7490 is to be used in a system, each ADT7490 is placed

in address select mode by strapping Pin 13 low on powerup.

The logic state of Pin 14 then determines the device’s

SMBus address. The logic of these pins is sampled on

powerup.

The device address is monitored from powerup but not

latched until the first valid SMBus transaction, more

precisely on the low-to-high transition at the beginning of

the eighth SCL pulse, when the serial bus address byte

matches the selected slave address. The selected slave

address is chosen using the ADDREN/ADDR SELECT

pins. Any attempted changes in the address have no effect

after this.

Table 7. HARD-WIRING THE ADT7490 SMBus

DEVICE ADDRESS

Pin 13 State

Pin 14 State

Address

0

Low (10 kW to GND)

0101100 (0x2C)

0

High (10 kW Pullup)

0101101 (0x2D)

1

Don’t Care

0101110 (0x2E)

Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the slave device. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, because a low-to-high

transition when the clock is high may be interpreted as a stop

signal. The number of data bytes that can be transmitted over

the serial bus in a single read or write operation is limited

only by what the master and slave devices can handle.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a stop

condition. In read mode, the master device overrides the

acknowledge bit by pulling the data line high during the low

period before the ninth clock pulse; this is known as no

acknowledge. The master takes the data line low during the

low period before the 10th clock pulse, and then high during

the 10th clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the

serial bus in one operation, but it is not possible to mix read

and write in one operation because the type of operation is

determined at the beginning and cannot subsequently be

changed without starting a new operation.

In the ADT7490, write operations contain either one or

two bytes, and read operations contain one byte. To write

data to one of the device data registers or read data from it,

the address pointer register must be set so that the correct

data register is addressed. Then data can be written into that

register or read from it. The first byte of a write operation

always contains an address that is stored in the address

pointer register. If data is to be written to the device, the write

operation must contain a second data byte that is written to

the register selected by the address pointer register.

This write operation is shown in Figure 18. The device

address is sent over the bus, and then R/W is set to 0. This

is followed by two data bytes. The first data byte is the

address of the internal data register to be written to, which

is stored in the address pointer register. The second data byte

is the data to be written to the internal data register.

When reading data from a register, there are two

possibilities:

1. If the ADT7490 address pointer register value is

unknown or not the desired value, it must first be

set to the correct value before data can be read

from the desired data register. This is done by

performing a write to the ADT7490 as before, but

only the data byte containing the register address

is sent because no data is written to the register.

This is shown in Figure 19.

A read operation is then performed consisting of

the serial bus address, R/W bit set to 1, followed

by the data byte read from the data register. This is

shown in Figure 20.

2. If the address pointer register is known to be

already at the desired address, data can be read

from the corresponding data register without first

writing to the address pointer register, as shown in

Figure 20.

Podobny numer części - ADT7490_16

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Analog Devices	ADT7490	1Mb / 76P	dBCool Remote Thermal Monitor and Fan Controller with PECI Interface Rev. 0

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Podobny opis - ADT7490_16

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ON Semiconductor	ADT7467	754Kb / 72P	Remote Thermal Monitor and Fan Controller May, 2012 ??Rev. 4
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	ADT7475_1110	639Kb / 58P	dbCOOL Remote Thermal Monitor and Fan Controller October, 2011 ??Rev. 5
Analog Devices	ADT7473	1Mb / 76P	dBCool Remote Thermal Monitor and Fan Controller REV. A
ON Semiconductor	ADT7460	645Kb / 46P	dBCOOL Remote Thermal Monitor and Fan Controller June, 2010 ??Rev. 5
ON Semiconductor	ADT7475	654Kb / 58P	dBCOOL Remote Thermal Monitor and Fan Controller June, 2009 ??Rev. 4

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