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ADS8324EB Arkusz danych(PDF) 3 Page - Texas Instruments |
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ADS8324EB Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 14 page ADS8324 3 SBAS172A www.ti.com ELECTRICAL CHARACTERISTICS: +VCC = +1.8V At –40 °C to +85°C, V REF = 0.9V, –In = 0.9V, fSAMPLE = 50kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. ADS8324E ADS8324EB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 14 ✻ Bits ANALOG INPUT Full-Scale Input Span +In – (–In) –VREF +VREF ✻✻ V Absolute Input Range +In –0.1 VCC + 0.1 ✻✻ V –In 0.8 +1.0 ✻✻ V Capacitance 25 ✻ pF Leakage Current 1 ✻ nA SYSTEM PERFORMANCE No Missing Codes 14 14 Bits Integral Linearity Error ±3 ±2 LSB Bipolar Zero Error ±4 ±8 ±2 ±4 LSB Bipolar Zero Error Drift ±0.1 ✻ µV/°C Gain Error ±4 ±8 ✻✻ LSB Gain Temperature Drift ±0.4 ✻ ppm/ °C Noise 60 ✻ µVrms Common-Mode Rejection Ratio at DCC 74 ✻ dB Power Supply Rejection Ratio +1.8V < VCC < +3.6V 3 ✻ LSB(1) SAMPLING DYNAMICS Conversion Time 16 ✻ Clk Cycles Acquisition Time 4.5 ✻ Clk Cycles Throughput Rate 50 ✻ kHz Clock Frequency Range 0.024 1.8 ✻✻ MHz DYNAMIC CHARACTERISTICS Total Harmonic Distortion VIN = 5Vp-p at 10kHz –84 –86 dB SINAD VIN = 5Vp-p at 10kHz 77 78 dB Spurious Free Dynamic Range VIN = 5Vp-p at 10kHz 85 86 dB SNR 78 ✻ dB REFERENCE INPUT Voltage Range 0.5 VCC/2 ✻✻ V Resistance CS = GND, fSAMPLE = 0Hz 5 ✻ G Ω CS = VCC 5 ✻ G Ω Current Drain 40 80 ✻✻ µA fSAMPLE = 10kHz 0.8 ✻ µA CS = VCC 0.1 3 ✻ µA DIGITAL INPUT/OUTPUT Logic Family CMOS ✻ Logic Levels: VIH IIH = +5µA 1.3 VCC + 0.3 ✻✻ V VIL IIL = +5µA –0.3 0.5 ✻✻ V VOH IOH = –250µA 1.4 ✻ V VOL IOL = 250µA 0.4 ✻ V Data Format Binary Two’s Complement ✻ POWER SUPPLY REQUIREMENTS VCC Specified Performance 1.8 ✻ V VCC Range(2) 1.8 3.6 ✻✻ V Quiescent Current 1400 1700 ✻✻ µA fSAMPLE = 10kHz(3, 4) 250 ✻ µA Power Dissipation VCC = 1.8V 2.5 3.0 ✻✻ mW Power Down CS = VCC 0.3 3.0 ✻✻ µA TEMPERATURE RANGE Specified Performance –40 +85 ✻✻ °C ✻ Specifications same as ADS8324E. NOTES: (1) LSB means Least Significant Bit. (2) See Typical Performance Curves for more information. (3) fCLK = 1.2MHz, CS = VCC for 216 clock cycles out of every 240. (4) See the Power Dissipation section for more information regarding lower sample rates. |
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